110 lines
3.6 KiB
Plaintext
110 lines
3.6 KiB
Plaintext
module FPLS
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title 'Feature test for F157
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Bob Lockhart Data I/O Redmond WA 4 Aug 1990'
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fpls device 'F157';
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C,L,H,X,Z = .C.,0,1,.X.,.Z.;
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Clk,Ena pin 1,11;
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I0,I1,I2,I3 pin 2,3,4,5;
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B0,B1,B2,B3,B4,B5 pin 6,7,8,9,12,19;
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F0,F1,F2,F3 pin 13,14,15,16;
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F4,F5 pin 17,18;
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mode = [B2,B1,B0];
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M_norm = [ 0, 0, 0];
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M_Preset = [ 1, 0, 0];
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M_Reset = [ 0, 1, 0];
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M_Load = [ 0, 0, 1];
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"Configure Flip/Flops F0 and F1 with ISTYPE statement
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F0 istype 'reg_JK ,invert';
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F1 istype 'reg_JKD,invert';
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F4 istype 'reg_JK ,invert';
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F5 istype 'reg_JK ,invert';
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equations
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"Output enable for bank A registers
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[F1,F0].OE = !Ena; " Enable controlled by pin 11
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"Clock Equations
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[F1,F0].C = Clk;
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"Flip/Flop control term
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F1.FC = I0;
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"Flip/Flop equations
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F0.J = I1;
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F0.K = I2;
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F1.J = I1;
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F1.K = I3;
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"Feedback equations
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B5 = F1.Q & F0.Q;
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"Preset,Reset, and Load
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[F1,F0].PR = B2;
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[F1,F0].RE = B1;
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[F1,F0].L = B0;
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@page
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test_vectors 'F1 in D type'
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([Clk,Ena,I0,I1,I2,I3,mode ] -> [!F0,!F1, B5])
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[ 0 , L , 0, 0, 0, 0,M_Reset ] -> [ 0 , 0 , 0 ]; "Reset
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[ C , L , 0, 0, 0, 0,M_norm ] -> [ 0 , 0 , 0 ];
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[ C , L , 0, 1, 0, 0,M_norm ] -> [ 1 , 1 , 1 ]; "High
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[ C , L , 0, 1, 1, 0,M_norm ] -> [ 0 , 1 , 0 ]; "Toggle F0
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[ C , L , 0, 1, 1, 0,M_norm ] -> [ 1 , 1 , 1 ]; "Toggle F0
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[ C , L , 0, 0, 0, 0,M_norm ] -> [ 1 , 0 , 0 ]; "Hold F0
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[ C , L , 0, 0, 1, 0,M_norm ] -> [ 0 , 0 , 0 ]; "Low
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[ 0 , L , 0, 0, 1, 0,M_Preset ] -> [ 1 , 1 , 1 ]; "Preset
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[ C , L , 0, 1, 1, 0,M_norm ] -> [ 0 , 1 , 0 ]; "Toggle F0
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test_vectors 'F1 in JK type'
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([Clk,Ena,I0,I1,I2,I3,mode ] -> [!F0,!F1, B5])
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[ 0 , L , 1, 0, 0, 0,M_Reset ] -> [ 0 , 0 , 0 ]; "Reset
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[ C , L , 1, 1, 1, 1,M_norm ] -> [ 1 , 1 , 1 ]; "Toggle
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[ C , L , 1, 1, 1, 1,M_norm ] -> [ 0 , 0 , 0 ]; "Toggle
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[ C , L , 1, 1, 0, 0,M_norm ] -> [ 1 , 1 , 1 ]; "High
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[ C , L , 1, 0, 0, 0,M_norm ] -> [ 1 , 1 , 1 ]; "Hold
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[ C , L , 1, 0, 1, 1,M_norm ] -> [ 0 , 0 , 0 ]; "Low
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[ C , H , 1, 1, 1, 1,M_norm ] -> [ Z , Z , 1 ]; "Toggle
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[ C , H , 1, 1, 1, 1,M_norm ] -> [ Z , Z , 0 ]; "Toggle
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test_vectors 'load'
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([Clk,Ena,I0,I1,I2,I3,mode ,!F0,!F1] -> [!F0,!F1, B5])
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[ 0 , L , 1, 0, 0, 0,M_Reset, X , X ] -> [ 0 , 0 , 0 ]; "Reset
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[ C , H , 1, 0, 0, 0,M_Load , 1 , 0 ] -> [ X , X , 0 ]; "Load
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[ 0 , L , 1, 0, 0, 0,M_norm , X , X ] -> [ 1 , 0 , 0 ]; "Test
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[ C , L , 1, 1, 1, 1,M_norm , X , X ] -> [ 0 , 1 , 0 ]; "Toggle
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equations
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"Output enable for bank B registers
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" [F5,F4].OE = [1,1];
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" Always enabled
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" Clock Equations
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[F5,F4].C = Clk;
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"Async Preset Equation
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[F5,F4].PR = !B3;
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"Equations for toggel counter
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[F4.J,F4.K] = [1,1];
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[F5.J,F5.K] = !F4.Q;
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test_vectors 'toggle counter'
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([Clk,Ena,B3] -> [F5,F4])
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[ 0 , 0 , 0] -> 0; " Reset
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[ C , 0 , 1] -> 1;
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[ C , 0 , 1] -> 2;
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[ C , 0 , 1] -> 3;
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[ C , 0 , 0] -> 0;
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[ C , 1 , 1] -> 1; " Output always enabled
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[ C , 0 , 1] -> 2;
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[ 0 , 0 , 0] -> 0; " Async Reset
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end
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