70 lines
1.8 KiB
Plaintext
70 lines
1.8 KiB
Plaintext
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DLsim Logic Circuit Analysis (Version 3.02)
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Copyright (c) 1990 CADsim Technologies. All rights reserved.
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Memory = 302312
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Signals = 103 Externals = 3 Elements = 107
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Probes = 9 Buses = 1 Macros = 1
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Sim length = 299 Step time = 1 Samples = 31
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$ decode3
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A C A N A L Y S I S
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////////%
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OOOOOOOOD
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01234567E
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C
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O
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D
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E
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_
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I
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N
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TIME
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0 ZZZZZZZZ0
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2 100000000
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20 100000001
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22 010000001
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40 010000002
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42 001000002
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60 001000003
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62 000100003
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80 000100004
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82 000010004
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100 000010005
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102 000001005
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120 000001006
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122 000000106
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140 000000107
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142 000000017
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160 000000016
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162 000000106
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180 000000105
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182 000001005
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200 000001004
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202 000010004
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220 000010003
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222 000100003
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240 000100002
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242 001000002
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260 001000001
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262 010000001
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280 010000000
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282 100000000
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299 100000000
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Simulation Completed Normally.
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