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SyncHome/trunk/workspace/01_EasyAbel/AHDL/SIMPLE.ABL
2023-03-13 08:36:51 +00:00

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module simple
title 'Simple ABEL example
Dan Poole Data I/O Corp 31 July 1991'
U7 device 'P14H4';
A1,A2,A3 pin 1,2,3;
N1,N2,N3 pin 4,5,6;
AND,NAND pin 15,16;
equations
AND = A1 & A2 & A3;
!NAND = N1 & N2 & N3;
test_vectors 'Test And Gate'
( [A1,A2,A3] -> AND )
[ 0, 0, 0] -> 0;
[ 1, 0, 0] -> 0;
[ 0, 1, 0] -> 0;
[ 0, 0, 1] -> 0;
[ 1, 1, 1] -> 1;
test_vectors 'Test Nand Gate'
( [N1,N2,N3] -> NAND )
[ 0, 0, 0] -> 1;
[ 1, 0, 0] -> 1;
[ 0, 1, 0] -> 1;
[ 0, 0, 1] -> 1;
[ 1, 1, 1] -> 0;
end simple