66 lines
4.0 KiB
Plaintext
66 lines
4.0 KiB
Plaintext
Source Device Load Description ABEL PLD 4.30
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File Type File
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actlow P22V10 actlow Example of active low output signals
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* barrel P20R8 barrel Set Notation in Equations
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* bcd7 P16P8 bcd7 7 Segment Truth Table
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* binbcd P16L8 binbcd Blackjack Machine Binary to BCD Converter
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* bjack P16R6 bjack Blackjack Machine Controler
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* cnt10p P16R4 cnt10p Test Vector Super-voltage Preload
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cnt507 F507 cnt507 TexIns PSG507 FPLS counter
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cnt600 E0600 cnt600 4-bit toggle flip-flop counter
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cntbuf E0320 cntbuf Test Case for 20 Pin PLDs
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cnt10rom RA10R8 cnt10rom Up/down counter State Machine in Reg PROM
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comp4 P16HD8 ic1 4-bit look-ahead comparator
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* comp4a F153 comp4a Relational Operators, Group Reduction
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count116 P16R8 count116 Counter Equations
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* count4 P16R4 count4 4-bit counter with 2 input mux
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* count4a P16R4 count4a Multiple equations for One Output
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* decade F105 decade Complement Array & Transition Equations
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demo600 E0600 demo600 4-bit counters and bidirectional buffer
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* dmux1t8 P16L8 dmux1t8 Sets in Equations
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* dstate2a P16R4 dstate State machine with illegal state recovery
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* dstate2b P16R4 dstate2b State machine with pin-to-pin description
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exampgds ISPGDS22 ispgds Example design for ISPGDS22 device
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fdback2 P22V10 fdback2 Register feedback and combo feedback
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* feedback P16HD8 feedback Simulator Example
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* findout P16L8 f1 Don't Cares in Simulation
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fpls F157 fpls Logic Sequencer Features
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fsm1 p22V10 fsm1 Finite state machine example
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fsm1_not P22V10 fsm1_not Finite state machine with active low bits
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* inreg P19L8R inreg Input registers use
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* langref ... ... Collections of ABEL-HDL examples
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* m6809a P14L4 m6809a Sets, Relational Operators
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* m6809b P14L4 m6809b Macros with Test Vectors
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* m6809c P14L4 m6809c Macros with Test Vectors
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m6809d P16HD8 m6809d Device type from Command Line
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* mac P16H8 m1 Macros and Declared Equations
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* mealy F105 mealy Mealy state machine description
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* moore P22V10 moore Moore state machine description
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* mux12t4 P16V8S mux12t4 12 to 4 multiplexer
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* muxadd P22V10 muxadd Blackjack Machine Adder
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* octalf P20X8 octalf Exclusive OR Factoring
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p20ra10 P20RA10 p20ra10 Combinational feedback clocking reg output
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pol1 P22V10 pol1 Often asked pin-to-pin polarity questions
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pol2 P22v10 pol2 Often asked detailed-description questions
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port P20RA10 port Test Vectors for Asyncronous PLDs
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* preset F167 preset Async Preset of 105 & 167
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* regfb P16R4 fb2 Simulator Example
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* reset22a P22V10 reset22a Register Preset and Reset (.RE and .PR)
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* sequence P16R4 sequence State Machine Example
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shiftcnt F159 ifl4 Control of D and JK Flip Flops
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simple P14H4 u7 A simple introductory ABEL example
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sn74190 P22V10 sn74190 Synch. 4-bit up/down counter
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* traffic F167 traffic Traffic signal controller (complement array)
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* traffic1 F167 traffic1 Traffic signal controller (@DCSET)
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* tsbuffer F153 tsb1 Bi-directional three state buffer
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* ttlload F159 ttl59 Loading Registers with Data
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xorpol P20X10 xorpol Polarity control with XORs
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* Example from ABEL Manual
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Langref.abl contains the following ABEL files:
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act_low1, act_low2, declare, detail1, detail2, foo_1, foo_2, foo_3,
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foo_5, foo_7, par_det, pin2pin, sm1, sm2, source, source2, statema,
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tt1, x1, x2, xorfact
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