509 lines
19 KiB
Plaintext
509 lines
19 KiB
Plaintext
" ***************************************************************
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" ZX81VID.ABL
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" ZX81 ULA replacement
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" ====================
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"
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" 10/25/97 Bodo Wenzel V1.0, creation
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" 07/11/97 Bodo Wenzel V1.1, correct ZX80 mode
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" ***************************************************************
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module zx81vid
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title 'ZX81 ULA replacement'
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" The device and pin definitions are in the file ZX81VID.PIN
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declarations
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" === pins and nodes ============================================
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" Some of the internal nodes are used for reducing logic (RL),
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" others because of the destination technology (DT).
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clock pin; " input
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n_phi pin istype 'reg';
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a15, a14 pin; " input
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a8, a7, a6, a5, a4, a3, a2, a1, a0 pin istype 'reg';
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qa8, qa7, qa6, qa5, qa4, qa3, qa2, qa1, qa0 node istype 'reg';
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" DT
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d7, d6, d5, d4, d3, d2, d1, d0 pin istype 'com';
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dd7, dd6, dd5, dd4, dd3, dd2, dd1, dd0 node istype 'com';
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" DT
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n_rd, n_wr, n_iorq, n_mreq, n_m1 pin; " input
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n_romcs, n_ramcs pin istype 'com';
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n_nmi pin istype 'com';
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n_halt pin; " input
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v_tp_o pin istype 'com';
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tape_i pin; " input
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usa_uk pin; " input
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kbd4, kbd3, kbd2, kbd1, kbd0 pin; " input
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io_wr_1 node istype 'com'; " RL
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hsync, vsync, nmi node istype 'com';
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db_oe node istype 'com'; " DT
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h_cnt8, h_cnt7, h_cnt6, h_cnt5, h_cnt4,
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h_cnt3, h_cnt2, h_cnt1, h_cnt0 node istype 'reg';
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h_cnt_res node istype 'com'; " RL
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row_cnt node istype 'com'; " RL
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v_tp_o_oe node istype 'com'; " DT
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fake node istype 'com';
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chr_pix7, chr_pix6, chr_pix5, chr_pix4,
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chr_pix3, chr_pix2, chr_pix1, chr_pix0 node istype 'reg';
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chr_pix_load node istype 'com'; " RL
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chr_inv node istype 'reg';
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chr_aen node istype 'reg';
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" === constants =================================================
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H_CNT_SET = [0,0,0,0,0,0,0,0,0]; " necessary for casting
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HSYNC_BEGIN = (H_CNT_SET+384);
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HSYNC_GAP = (H_CNT_SET+32);
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H_CNT_MAX = (H_CNT_SET+413);
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" === other declarations ========================================
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ddb_4_0 = [dd4..dd0];
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ddb = [dd7..dd0];
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db_4_0 = [d4..d0];
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db_5_0 = [d5..d0];
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db = [d7..d0];
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kb = [kbd4..kbd0];
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h_cnt = [h_cnt8..h_cnt0];
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chr_code = [qa8..qa3];
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chr_row = [qa2..qa0];
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ab = [a8..a0];
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ab_code = [a8..a3];
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ab_row = [a2..a0];
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chr_pix = [chr_pix7..chr_pix0];
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x = .x.;
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c = .c.;
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k = .k.;
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z = .z.;
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x6 = [x, x, x, x, x, x];
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x8 = [x, x, x, x, x, x, x, x];
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k5 = [k, k, k, k, k];
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z3 = [z, z, z];
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z6 = [z, z, z, z, z, z];
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z8 = [z, z, z, z, z, z, z, z];
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" === equations =================================================
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equations
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" --- clock divider ---------------------------------------------
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" Divides the clock by 2 producing the cpu clock.
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n_phi.clk = clock;
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n_phi := !n_phi;
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" --- memory selects --------------------------------------------
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" ROM is selected if cpu accesses adress range 00000H to 03FFFH,
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" else RAM.
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when !a15 & !a14 then
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!n_romcs = !n_mreq;
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else
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!n_ramcs = !n_mreq;
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" --- io ports --------------------------------------------------
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" Two latches are used to control the video logic.
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" Together with the keyboard scan lines the tape input and the
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" jumper for the vsync frequency is sampled.
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" If the cpu is to be faked with NOP zeroes are output.
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io_wr_1 = !n_iorq & !n_wr & !a1;
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vsync = (!n_iorq & !n_rd & !a0 & !nmi)
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# (vsync & !(!n_iorq & !n_wr));
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nmi = (!n_iorq & !n_wr & !a0)
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# (nmi & !io_wr_1);
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dd7 = tape_i & !n_iorq;
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dd6 = usa_uk & !n_iorq;
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dd5 = 0 & !n_iorq;
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ddb_4_0 = kb & !n_iorq;
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db_oe = chr_aen & !n_m1
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# (!n_iorq & !n_rd & !a0);
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db.oe = db_oe;
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" The equations of the nodes and pins have to be equal! DT
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d7 = tape_i & !n_iorq;
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d6 = usa_uk & !n_iorq;
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d5 = 0 & !n_iorq;
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db_4_0 = kb & !n_iorq;
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" --- video -----------------------------------------------------
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" The h_cnt divides the clock by 414 generating the signal n_nmi
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" (if enabled) and hsync. Both signals may glitch!
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" If the cpu activates vsync the h_cnt is reset synchronously.
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" In ZX80 mode (and for using ASZMIC) the h_cnt is set by INTACK
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" (iorq and m1) synchronously to the end of line.
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" At the output v_tp_o should be a resistor ladder to produce the
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" correct levels (0=sync, z=black, 1=white).
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" The shift register is loaded if pattern data are ready
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" otherwise it is shifted.
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h_cnt.clk = clock;
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when !n_iorq & !n_m1 then
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h_cnt := HSYNC_BEGIN-HSYNC_GAP;
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else
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h_cnt := (h_cnt+1) & !h_cnt_res;
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h_cnt_res = (h_cnt==H_CNT_MAX) # vsync;
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hsync = h_cnt>=HSYNC_BEGIN;
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n_nmi = !(nmi & hsync);
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v_tp_o_oe = vsync # hsync # (chr_pix7==0);
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v_tp_o.oe = v_tp_o_oe;
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when vsync # hsync then
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v_tp_o = 0;
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else
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v_tp_o = 1;
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chr_pix_load = chr_aen & !n_mreq & n_m1 & !n_phi;
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chr_pix.clk = clock;
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when chr_pix_load then
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chr_pix := db $ chr_inv;
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else
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chr_pix := [chr_pix6..chr_pix0, 0];
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" --- character generator ---------------------------------------
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" Faking the cpu is done if an opcode fetch at addresses
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" >= 08000H appears without halted cpu or D6=1.
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" If a character pattern is to be loaded the signal chr_aen is
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" activated. It will enable the output of the pattern address.
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" The flipflops for character inversion and code are loaded one
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" clock after raising fake.
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" The row counter is synchronously reset by vsync and is
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" incremented at the end of every line.
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fake = !n_phi & !n_mreq & !n_m1 & a15 & n_halt & !d6;
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chr_aen.clk = clock;
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chr_aen := fake
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# (chr_aen & (n_phi # n_mreq));
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chr_inv.clk = clock;
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when fake then
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chr_inv := d7;
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else
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chr_inv := chr_inv;
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chr_code.clk = clock;
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when fake then
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chr_code := db_5_0;
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else
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chr_code := chr_code;
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row_cnt = (h_cnt==HSYNC_BEGIN);
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chr_row.clk = clock;
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when row_cnt then
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chr_row := (chr_row+1) & !vsync;
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else
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chr_row := chr_row & !vsync;
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ab.oe = chr_aen & n_m1;
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" The equations of the pins and nodes have to be equal! DT
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ab.clk = clock;
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when fake then
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ab_code := db_5_0;
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else
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ab_code := chr_code;
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when row_cnt then
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ab_row := (chr_row+1) & !vsync;
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else
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ab_row := chr_row & !vsync;
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" === test vectors ==============================================
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" They probably have to be edited every time changes in the
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" equations are made!
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" --- clock divider ---------------------------------------------
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test_vectors 'clock divider'
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([clock] -> [n_phi])
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@repeat 10 {
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[c ] -> [x ];
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}
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" --- memory selects --------------------------------------------
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test_vectors 'memory selects'
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([n_mreq, a15, a14] -> [n_romcs, n_ramcs])
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[1 , 0 , 0 ] -> [1 , 1 ];
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[1 , 0 , 1 ] -> [1 , 1 ];
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[1 , 1 , 0 ] -> [1 , 1 ];
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[1 , 1 , 1 ] -> [1 , 1 ];
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[0 , 0 , 0 ] -> [0 , 1 ];
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[1 , 0 , 0 ] -> [1 , 1 ];
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[0 , 0 , 1 ] -> [1 , 0 ];
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[1 , 0 , 1 ] -> [1 , 1 ];
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[0 , 1 , 0 ] -> [1 , 0 ];
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[1 , 1 , 0 ] -> [1 , 1 ];
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[0 , 1 , 1 ] -> [1 , 0 ];
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[1 , 1 , 1 ] -> [1 , 1 ];
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" --- io ports --------------------------------------------------
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test_vectors 'video control latches'
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([n_iorq, n_rd, n_wr, a1, a0] -> [vsync, nmi])
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[0 , 1 , 0 , 0 , 1 ] -> [0 , 0 ];
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[1 , k , k , k , k ] -> [0 , 0 ];
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[k , 1 , 1 , k , k ] -> [0 , 0 ];
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[0 , 0 , 1 , 0 , 0 ] -> [1 , 0 ];
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[1 , k , k , k , k ] -> [1 , 0 ];
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[0 , 1 , 0 , 1 , 1 ] -> [0 , 0 ];
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[1 , k , k , k , k ] -> [0 , 0 ];
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[0 , 0 , 1 , 1 , 0 ] -> [1 , 0 ];
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[1 , k , k , k , k ] -> [1 , 0 ];
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[0 , 1 , 0 , 1 , 1 ] -> [0 , 0 ];
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[1 , k , k , k , k ] -> [0 , 0 ];
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[0 , 1 , 0 , 1 , 0 ] -> [0 , 1 ];
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[1 , k , k , k , k ] -> [0 , 1 ];
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[0 , 0 , 1 , 1 , 0 ] -> [0 , 1 ];
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[1 , k , k , k , k ] -> [0 , 1 ];
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[0 , 1 , 0 , 0 , 1 ] -> [0 , 0 ];
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test_vectors 'keyboard etc. input'
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([n_iorq, n_rd, a0, tape_i, usa_uk, kb ] -> [db ])
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[1 , k , k , k , k , k5 ] -> [z8 ];
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[k , 1 , k , k , k , k5 ] -> [z8 ];
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[k , k , 1 , k , k , k5 ] -> [z8 ];
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[0 , 0 , 0 , 0 , 0 , ^b11110] -> [^h1E];
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[1 , k , k , k , k , k5 ] -> [z8 ];
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[0 , 0 , 0 , 1 , 0 , ^b11101] -> [^h9D];
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[1 , k , k , k , k , k5 ] -> [z8 ];
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[0 , 0 , 0 , 0 , 1 , ^b11011] -> [^h5B];
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[1 , k , k , k , k , k5 ] -> [z8 ];
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[0 , 0 , 0 , 1 , 1 , ^b10111] -> [^hD7];
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[1 , k , k , k , k , k5 ] -> [z8 ];
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[0 , 0 , 0 , 0 , 1 , ^b01111] -> [^h4F];
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[1 , k , k , k , k , k5 ] -> [z8 ];
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[0 , 0 , 0 , 1 , 0 , ^b10101] -> [^h95];
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[1 , k , k , k , k , k5 ] -> [z8 ];
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[0 , 0 , 0 , 0 , 0 , ^b01010] -> [^h0A];
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[1 , k , k , k , k , k5 ] -> [z8 ];
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" --- video -----------------------------------------------------
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test_vectors 'sync and nmi'
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([clock, n_m1, n_iorq, n_rd, n_wr, a1, a0] ->
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[h_cnt, v_tp_o, n_nmi])
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" clk m1 iorq rd wr a1 a0 -> h_cnt v_tp_o nmi
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[c , 1, 0 , 0, 1, k, 0] -> [ x , 0 , 1 ];
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[0 , 1, 0 , 1, 0, 1, 0] -> [ 0 , 1 , 1 ];
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@repeat 382 {
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[c , 1, 1 , x, x, x, x] -> [ x , 1 , 1 ];
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}
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[c , 1, 1 , x, x, x, x] -> [383 , 1 , 1 ];
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[c , 1, 1 , x, x, x, x] -> [384 , 0 , 0 ];
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@repeat 20 {
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[c , 1, 1 , x, x, x, x] -> [ x , 0 , 0 ];
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}
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[0 , 1, 0 , 1, 0, 0, 1] -> [404 , 0 , 1 ];
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@repeat 8 {
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[c , 1, 1 , x, x, x, x] -> [ x , 0 , 1 ];
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}
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[c , 1, 1 , x, x, x, x] -> [413 , 0 , 1 ];
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[c , 1, 1 , x, x, x, x] -> [ 0 , 1 , 1 ];
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" clk m1 iorq rd wr a1 a0 -> h_cnt v_tp_o nmi
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@repeat 12 {
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[c , 1, 1 , x, x, x, x] -> [ x , 1 , 1 ];
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}
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[c , 1, 1 , x, x, x, x] -> [ 13 , 1 , 1 ];
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[c , 0, 0 , x, x, x, x] -> [352 , 1 , 1 ];
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[c , 0, 0 , x, x, x, x] -> [352 , 1 , 1 ];
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[c , 0, 0 , x, x, x, x] -> [352 , 1 , 1 ];
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@repeat 31 {
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[c , 1, 1 , x, x, x, x] -> [ x , 1 , 1 ];
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}
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@repeat 29 {
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[c , 1, 1 , x, x, x, x] -> [ x , 0 , 1 ];
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}
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[c , 1, 1 , x, x, x, x] -> [413 , 0 , 1 ];
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[c , 1, 1 , x, x, x, x] -> [ 0 , 1 , 1 ];
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" The video output is tested with the character generator...
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" --- character generator ---------------------------------------
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test_vectors 'fake signal'
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([clock, n_iorq, n_mreq, n_m1, a15, n_halt, d6] -> [n_phi, fake])
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" if the check fails on n_phi, un/comment the following line
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" [c , 1 , 1 , x , x , x , x ] -> [1 , 0 ];
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[c , 1 , 1 , x , x , x , x ] -> [0 , 0 ];
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[0 , 1 , 1 , 0 , 1 , 1 , 0 ] -> [0 , 0 ];
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[0 , 1 , 0 , 1 , 1 , 1 , 0 ] -> [0 , 0 ];
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[0 , 1 , 0 , 0 , 0 , 1 , 0 ] -> [0 , 0 ];
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[0 , 1 , 0 , 0 , 1 , 0 , 0 ] -> [0 , 0 ];
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[0 , 1 , 0 , 0 , 1 , 1 , 1 ] -> [0 , 0 ];
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[c , 1 , 1 , x , x , x , x ] -> [1 , 0 ];
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[0 , 1 , 0 , 0 , 1 , 1 , 0 ] -> [1 , 0 ];
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[c , 1 , 0 , 0 , 1 , 1 , 0 ] -> [0 , 1 ];
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test_vectors 'catch character code'
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([clock, n_iorq, n_mreq, n_m1, a15, n_halt, db] ->
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[n_phi, db, chr_inv, ab_code, chr_aen, chr_pix])
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" clk io mrq m1 a15 hlt db -> phi db inv code aen pix
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[c , 1, 1 , 1, x , x , z8 ] -> [1 , x8 , x , z6 , x , x8 ];
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[c , 1, 0 , 1, x , x , x8 ] -> [0 , x8 , x , x6 , x , x8 ];
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[c , 1, 0 , 1, x , x , x8 ] -> [1 , x8 , x , x6 , 0 , x8 ];
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[c , 1, 1 , 1, x , x , z8 ] -> [0 , x8 , x , z6 , 0 , x8 ];
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[c , 1, 1 , 0, 1 , 1 , z8 ] -> [1 , z8 , x , z6 , 0 , x8 ];
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[c , 1, 0 , 0, 1 , 1 , x8 ] -> [0 , z8 , x , z6 , 0 , x8 ];
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[c , 1, 0 , 0, 1 , 1 , ^h15] -> [1 , ^h00, 0 , z6 , 1 , x8 ];
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[c , 1, 0 , 0, 1 , 1 , z8 ] -> [0 , ^h00, 0 , z6 , 1 , x8 ];
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[0 , 1, 1 , 1, x , 1 , z8 ] -> [0 , z8 , 0 , ^h15, 1 , x8 ];
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[c , 1, 1 , 1, x , 1 , z8 ] -> [1 , z8 , 0 , ^h15, 1 , x8 ];
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[c , 1, 0 , 1, x , 1 , x8 ] -> [0 , z8 , 0 , ^h15, 1 , x8 ];
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[c , 1, 0 , 1, x , 1 , ^h3C] -> [1 , z8 , 0 , z6 , 0 , ^h3C];
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[c , 1, 1 , 1, x , 1 , z8 ] -> [0 , z8 , 0 , z6 , 0 , ^h78];
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" clk io mrq m1 a15 hlt db -> phi db inv code aen pix
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[c , 1, 1 , 0, 1 , 1 , z8 ] -> [1 , z8 , 0 , z6 , 0 , ^hF0];
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[c , 1, 0 , 0, 1 , 1 , x8 ] -> [0 , z8 , 0 , z6 , 0 , ^hE0];
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[c , 1, 0 , 0, 1 , 1 , ^hAA] -> [1 , ^h00, 1 , z6 , 1 , ^hC0];
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[c , 1, 0 , 0, 1 , 1 , z8 ] -> [0 , ^h00, 1 , z6 , 1 , ^h80];
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[0 , 1, 1 , 1, x , 1 , z8 ] -> [0 , z8 , 1 , ^h2A, 1 , ^h80];
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[c , 1, 1 , 1, x , 1 , z8 ] -> [1 , z8 , 1 , ^h2A, 1 , ^h00];
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[c , 1, 0 , 1, x , 1 , x8 ] -> [0 , z8 , 1 , ^h2A, 1 , ^h00];
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[c , 1, 0 , 1, x , 1 , ^h5A] -> [1 , z8 , 1 , z6 , 0 , ^hA5];
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[c , 1, 1 , 1, x , 1 , z8 ] -> [0 , z8 , 1 , z6 , 0 , ^h4A];
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[c , 1, 1 , 0, 1 , 1 , z8 ] -> [1 , z8 , 1 , z6 , 0 , ^h94];
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[c , 1, 0 , 0, 1 , 1 , x8 ] -> [0 , z8 , 1 , z6 , 0 , ^h28];
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[c , 1, 0 , 0, 1 , 1 , ^h76] -> [1 , z8 , x , z6 , 0 , ^h50];
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[c , 1, 0 , 0, 1 , 1 , z8 ] -> [0 , z8 , x , z6 , 0 , ^hA0];
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[0 , 1, 1 , 1, x , 1 , z8 ] -> [0 , z8 , x , z6 , 0 , ^hA0];
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[c , 1, 1 , 1, x , 1 , z8 ] -> [1 , z8 , x , z6 , 0 , ^h40];
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[c , 1, 0 , 1, x , 1 , x8 ] -> [0 , z8 , x , z6 , 0 , ^h80];
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[c , 1, 0 , 1, x , 1 , x8 ] -> [1 , z8 , x , z6 , 0 , ^h00];
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[c , 1, 1 , 1, x , 1 , z8 ] -> [0 , z8 , x , z6 , 0 , ^h00];
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" clk io mrq m1 a15 hlt db -> phi db inv code aen pix
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[c , 1, 1 , 0, 1 , 1 , z8 ] -> [1 , z8 , x , z6 , 0 , ^h00];
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[c , 1, 0 , 0, 1 , 1 , x8 ] -> [0 , z8 , x , z6 , 0 , ^h00];
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[c , 1, 0 , 0, 1 , 1 , ^h96] -> [1 , ^h00, 1 , z6 , 1 , ^h00];
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[c , 1, 0 , 0, 1 , 1 , z8 ] -> [0 , ^h00, 1 , z6 , 1 , ^h00];
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[0 , 1, 1 , 1, x , 1 , z8 ] -> [0 , z8 , 1 , ^h16, 1 , ^h00];
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[c , 1, 1 , 1, x , 1 , z8 ] -> [1 , z8 , 1 , ^h16, 1 , ^h00];
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[c , 1, 0 , 1, x , 1 , x8 ] -> [0 , z8 , 1 , ^h16, 1 , ^h00];
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[c , 1, 0 , 1, x , 1 , ^hC3] -> [1 , z8 , 1 , z6 , 0 , ^h3C];
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[c , 1, 1 , 1, x , 1 , z8 ] -> [0 , z8 , 1 , z6 , 0 , ^h78];
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[c , 1, 1 , 0, 0 , 1 , z8 ] -> [1 , z8 , 1 , z6 , 0 , ^hF0];
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[c , 1, 0 , 0, 0 , 1 , x8 ] -> [0 , z8 , 1 , z6 , 0 , ^hE0];
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[c , 1, 0 , 0, 0 , 1 , x8 ] -> [1 , z8 , x , z6 , 0 , ^hC0];
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[c , 1, 0 , 0, 0 , 1 , z8 ] -> [0 , z8 , x , z6 , 0 , ^h80];
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[0 , 1, 1 , 1, x , 1 , z8 ] -> [0 , z8 , x , z6 , 0 , ^h80];
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[c , 1, 1 , 1, x , 1 , z8 ] -> [1 , z8 , x , z6 , 0 , ^h00];
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[c , 1, 0 , 1, x , 1 , x8 ] -> [0 , z8 , x , z6 , 0 , ^h00];
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[c , 1, 0 , 1, x , 1 , x8 ] -> [1 , z8 , x , z6 , 0 , ^h00];
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[c , 1, 1 , 1, x , 1 , z8 ] -> [0 , z8 , x , z6 , 0 , ^h00];
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test_vectors 'combined video output'
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([clock, n_iorq, n_mreq, n_m1, a15, n_halt, db ] ->
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[n_phi, v_tp_o])
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" clk io mrq m1 a15 halt db -> phi, v_tp_o
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[c , 1, 1 , 0, 1 , 1 , z8 ] -> [1 , 1 ];
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[c , 1, 0 , 0, 1 , 1 , x8 ] -> [0 , 1 ];
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[c , 1, 0 , 0, 1 , 1 , ^hAA] -> [1 , 1 ];
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[c , 1, 0 , 0, 1 , 1 , z8 ] -> [0 , 1 ];
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[c , 1, 1 , 1, x , 1 , z8 ] -> [1 , 1 ];
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[c , 1, 0 , 1, x , 1 , x8 ] -> [0 , 1 ];
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[c , 1, 0 , 1, x , 1 , ^h5A] -> [1 , z ];
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[c , 1, 1 , 1, x , 1 , z8 ] -> [0 , 1 ];
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|
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[c , 1, 1 , 0, 1 , 1 , z8 ] -> [1 , z ];
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[c , 1, 0 , 0, 1 , 1 , x8 ] -> [0 , 1 ];
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[c , 1, 0 , 0, 1 , 1 , ^h76] -> [1 , 1 ];
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[c , 1, 0 , 0, 1 , 1 , z8 ] -> [0 , z ];
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[c , 1, 1 , 1, x , 1 , z8 ] -> [1 , 1 ];
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[c , 1, 0 , 1, x , 1 , x8 ] -> [0 , z ];
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[c , 1, 0 , 1, x , 1 , x8 ] -> [1 , 1 ];
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[c , 1, 1 , 1, x , 1 , z8 ] -> [0 , 1 ];
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|
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test_vectors 'row counter'
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([clock, n_mreq, n_m1, n_iorq, n_rd, n_wr, a15, a1, a0,
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n_halt, db] -> [n_phi, h_cnt, ab_row])
|
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" clk mrq m1 iorq rd wr a15 a1 a0 hlt db -> ph cnt row
|
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[c , 1 , 1, 0 , 0, 1, x , 1, 0, x , x8 ] -> [1, 0 , z3 ];
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[c , 1 , 1, 0 , 1, 0, x , 1, 1, x , x8 ] -> [0, 1 , z3 ];
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@repeat 187 {
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|
[c , 1 , x, 1 , x, x, x , x, x, x , x8 ] -> [1, x , z3 ];
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[c , 1 , x, 1 , x, x, x , x, x, x , x8 ] -> [0, x , z3 ];
|
|
}
|
|
|
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@const row=0;
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@repeat 7 {
|
|
" clk mrq m1 iorq rd wr a15 a1 a0 hlt db -> ph cnt row
|
|
[c , 1 , 0, 1 , x, x, 1 , x, x, 1 , z8 ] -> [1, 376, z3 ];
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[c , 0 , 0, 1 , x, x, 1 , x, x, 1 , x8 ] -> [0, 377, z3 ];
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[c , 0 , 0, 1 , x, x, 1 , x, x, 1 , ^h99] -> [1, 378, z3 ];
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[c , 0 , 0, 1 , x, x, 1 , x, x, 1 , z8 ] -> [0, 379, z3 ];
|
|
[0 , 1 , 1, 1 , x, x, x , x, x, 1 , z8 ] -> [0, 379, row];
|
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[c , 1 , 1, 1 , x, x, x , x, x, 1 , z8 ] -> [1, 380, row];
|
|
[c , 0 , 1, 1 , x, x, x , x, x, 1 , x8 ] -> [0, 381, row];
|
|
[c , 0 , 1, 1 , x, x, x , x, x, 1 , x8 ] -> [1, 382, z3 ];
|
|
[c , 1 , 1, 1 , x, x, x , x, x, 1 , z8 ] -> [0, 383, z3 ];
|
|
|
|
@const row=row+1;
|
|
[c , 1 , 0, 1 , x, x, 1 , x, x, 1 , z8 ] -> [1, 384, z3 ];
|
|
[c , 0 , 0, 1 , x, x, 1 , x, x, 1 , x8 ] -> [0, 385, z3 ];
|
|
[c , 0 , 0, 1 , x, x, 1 , x, x, 1 , ^h99] -> [1, 386, z3 ];
|
|
[c , 0 , 0, 1 , x, x, 1 , x, x, 1 , z8 ] -> [0, 387, z3 ];
|
|
[0 , 1 , 1, 1 , x, x, x , x, x, 1 , z8 ] -> [0, 387, row];
|
|
[c , 1 , 1, 1 , x, x, x , x, x, 1 , z8 ] -> [1, 388, row];
|
|
[c , 0 , 1, 1 , x, x, x , x, x, 1 , x8 ] -> [0, 389, row];
|
|
[c , 0 , 1, 1 , x, x, x , x, x, 1 , x8 ] -> [1, 390, z3 ];
|
|
[c , 1 , 1, 1 , x, x, x , x, x, 1 , z8 ] -> [0, 391, z3 ];
|
|
|
|
@repeat 199 {
|
|
[c , 1 , x, 1 , x, x, x , x, x, x , x8 ] -> [1, x , z3 ];
|
|
[c , 1 , x, 1 , x, x, x , x, x, x , x8 ] -> [0, x , z3 ];
|
|
}
|
|
}
|
|
|
|
" clk mrq m1 iorq rd wr a15 a1 a0 hlt db -> ph cnt row
|
|
[c , 1 , x, 1 , x, x, x , x, x, x , x8 ] -> [1, 376, z3 ];
|
|
[c , 1 , x, 1 , x, x, x , x, x, x , x8 ] -> [0, 377, z3 ];
|
|
[c , 1 , x, 1 , x, x, x , x, x, x , x8 ] -> [1, 378, z3 ];
|
|
[c , 1 , x, 1 , x, x, x , x, x, x , x8 ] -> [0, 379, z3 ];
|
|
[c , 1 , 0, 1 , x, x, 1 , x, x, 1 , z8 ] -> [1, 380, z3 ];
|
|
[c , 0 , 0, 1 , x, x, 1 , x, x, 1 , x8 ] -> [0, 381, z3 ];
|
|
[c , 0 , 0, 1 , x, x, 1 , x, x, 1 , ^h99] -> [1, 382, z3 ];
|
|
[c , 0 , 0, 1 , x, x, 1 , x, x, 1 , z8 ] -> [0, 383, z3 ];
|
|
[0 , 1 , 1, 1 , x, x, x , x, x, 1 , z8 ] -> [0, 383, 7 ];
|
|
[c , 1 , 1, 1 , x, x, x , x, x, 1 , z8 ] -> [1, 384, 7 ];
|
|
[c , 0 , 1, 1 , x, x, x , x, x, 1 , x8 ] -> [0, 385, 0 ];
|
|
[c , 0 , 1, 1 , x, x, x , x, x, 1 , x8 ] -> [1, 386, z3 ];
|
|
[c , 1 , 1, 1 , x, x, x , x, x, 1 , z8 ] -> [0, 387, z3 ];
|
|
|
|
" === end =======================================================
|
|
|
|
end
|