153 lines
5.8 KiB
Plaintext
153 lines
5.8 KiB
Plaintext
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OPL2PLA - OPAL design entry compiler V016
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Copyright (c) National Semiconductor Corporation 1991,1992
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Input Pins
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==========
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Pin name pin number arch visible default
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-------- ---------- ---- ------- -------
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clk 1 com visible
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reset 2 com visible
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/oe 11 com visible
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Feedback Pins
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=============
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Pin name pin number arch visible default
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-------- ---------- ---- ------- -------
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reg_hold 14 reg visible hold
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set notations
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=============
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in_state = [sb1,sb2,sb3,sb4]
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Statebit Pins
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=============
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Pin name pin number arch visible default
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-------- ---------- ---- ------- -------
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sb1 15 reg visible rst
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sb2 16 reg visible rst
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sb3 17 reg visible rst
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sb4 18 reg visible rst
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Dot extensions
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==============
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Pin name pin number arch visible default
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-------- ---------- ---- ------- -------
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reg_hold.c com visible rst
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sb4.c com visible rst
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sb3.c com visible rst
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sb2.c com visible rst
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sb1.c com visible rst
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reg_hold.oe com visible rst
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sb4.oe com visible rst
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sb3.oe com visible rst
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sb2.oe com visible rst
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sb1.oe com visible rst
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state definition
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================
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State_name state assignment branching
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---------- ---------------- ---------
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ALL if
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s0 0000 0000 goto
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s1 0001 0001 goto
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s2 0002 0010 goto
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s3 0003 0011 goto
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s4 0004 0100 goto
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s5 0005 0101 goto
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s6 0006 0110 goto
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s7 0007 0111 goto
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s8 0008 1000 goto
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s9 0009 1001 goto
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UNDEFINED goto
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Present State Possible next state(s)
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------------- ----------------------
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ALL s0
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s0 s1
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s1 s2
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s2 s3
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s3 s4
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s4 s5
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s5 s6
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s6 s7
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s7 s8
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s8 s9
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s9 s0
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UNDEFINED s0
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------------------------------------------------------------------------------
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PLAMIN -- PLA Minimizer (V002)
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Copyright (c) National Semiconductor Corporation, 1992
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Device: GAL16V8
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Architecture: PAL
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Product Term Polarity: SELECTABLE
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Minimization Level: NORMAL
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ESPRESSO Command Line: espresso -Dso_both state_1.pla > TMP1.$$$
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Minimization Time: 0:03
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Product Terms: 42 / 25 (59.5%)
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------------------------------------------------------------------------------
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EQN2JED - Boolean Equations to JEDEC file assembler (Version V059)
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Copyright (c) National Semiconductor Corporation 1990,1991
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Document file for state_1.eqn
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Device: 16V8
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Pin Label Type
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--- ----- ----
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1 clk clock pin
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2 reset pos,com input
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11 /oe enable pin
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14 reg_hold pos,trst,reg feedback
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15 sb1 pos,trst,reg feedback(bidir)
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16 sb2 pos,trst,reg feedback(bidir)
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17 sb3 pos,trst,reg feedback(bidir)
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18 sb4 pos,trst,reg feedback(bidir)
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EQN2JED - Boolean Equations to JEDEC file assembler (Version V059)
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Copyright (c) National Semiconductor Corporation 1990,1991
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Device Utilization:
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No of dedicated inputs used : 1/8 (12.5%)
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No of feedbacks used : 5/8 (62.5%)
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------------------------------------------
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Pin Label Terms Usage
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------------------------------------------
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18 sb4 1/8 (12.5%)
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17 sb3 1/8 (12.5%)
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16 sb2 2/8 (25.0%)
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15 sb1 1/8 (12.5%)
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14 reg_hold 5/8 (62.5%)
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------------------------------------------
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Total Terms 15/64 (23.4%)
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------------------------------------------
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EQN2JED - Boolean Equations to JEDEC file assembler (Version V059)
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Copyright (c) National Semiconductor Corporation 1990,1991
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Chip diagram (DIP)
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._____ _____.
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| \__/ |
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clk | 1 20 | VCC
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reset | 2 19 |
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| 3 18 | sb4
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| 4 17 | sb3
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| 5 16 | sb2
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| 6 15 | sb1
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| 7 14 | reg_hold
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| 8 13 |
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| 9 12 |
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GND | 10 11 | /oe
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|______________|
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