82 lines
3.4 KiB
NASM
82 lines
3.4 KiB
NASM
*******************************************************************************
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; MAIN.ASM
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;*******************************************************************************
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; Copyright (c) 2002 SofTec Microsystems
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; http://www.softecmicro.com/
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;*******************************************************************************
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;
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; ADC Sample for SofTec Microsystems' IDB-HC08JK Demo Board (MC68HC908JK3 installed)
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;
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; This program configures the A/D peripheral to convert on A/D channel 9
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; (PTD2, connected to the potentiometer) and displays the results on the LEDs
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; on PTB[7..4], PTD[7..4]. Make sure that all of the "LED ENABLE" jumpers and the
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; "POTENTIOMETER ENABLE" jumper are inserted.
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;*******************************************************************************
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XDEF Entry, irq_isr, main, _Startup
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;*******************************************************************************
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; Registers definition
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;*******************************************************************************
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PTB EQU $0001 ; Port B data register
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PTD EQU $0003 ; Port D data register
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DDRB EQU $0005 ; Port B data direction register
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DDRD EQU $0007 ; Port D data direction register
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CONFIG1 EQU $001F ; Configuration register 1
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ADSCR EQU $003C ; ADC status and control register
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ADR EQU $003D ; ADC data register
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ADICLK EQU $003E ; ADC input clock register
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;*******************************************************************************
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DEFAULT_ROM SECTION
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;*******************************************************************************
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; Peripheral Initialization
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;*******************************************************************************
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_Startup:
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init:
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bset 0, CONFIG1 ; Disables COP
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mov #$F0, DDRB ; Configures port B[7..4] as output
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mov #$F0, DDRD ; Configures port D[7..4] as output
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mov #$29, ADSCR ; Enables ADC channel 9
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mov #$40, ADICLK ; ADC input clock / 4
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;*******************************************************************************
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; Entry Point
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;*******************************************************************************
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Entry:
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main:
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rsp ; SP <- 0xFF
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cli ; Enables global interrupts
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;bsr init ; Peripheral initialization
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main_loop:
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brclr 7, ADSCR ,main_loop ; Waits for ADC end of conversion
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lda ADR ; Reads ADC value
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sta PTD ; Writes the high nibble on port D[7..4]
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nsa
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sta PTB ; Writes the low nibble on port B[7..4]
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bra main_loop ; Forever
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;*******************************************************************************
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; IRQ Interrupt Handler
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; ---------------------
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; This subroutine is needed to implement the "Halt" debugging command.
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;*******************************************************************************
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irq_isr:
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bil irq_isr ; Waits for the IRQ signal to go high
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swi ; Jumps to monitor code
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rti
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END
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