160 lines
4.7 KiB
NASM
160 lines
4.7 KiB
NASM
; Emulated 65C02 SOC
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;
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; By Daryl Rictor (c)2012
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;
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; 16k - 256 byte RAM
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; 48k ROM (in flash)
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; IO @ 3Fxx
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;******************************************************************************
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; include AVRASM definitions
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;******************************************************************************
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.include "m1284Pdef.inc"
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;******************************************************************************
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; Set Register definitions
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;******************************************************************************
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.def i = R16
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.def j = R17
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.def zero = R2
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.def one = R3
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.def mmap = R4
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.def free1 = R12 ; unused register pair
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.def free2 = R13
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;******************************************************************************
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; Load Lower Flash Tables starting at 0x1B00 (below ROM image)
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;******************************************************************************
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.include "av2sr.inc"
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.include "sr2av.inc"
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.include "opcjmp.inc"
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.include "ioexe.inc"
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.include "sbcrom.inc"
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;******************************************************************************
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; Program Starts here on Reset
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;******************************************************************************
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STARTUP: ; first line executed after reset
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CLI ; disable interupts
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;******************************************************************************
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; Initialize the I/O Ports
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;******************************************************************************
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; port A pins
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ldi i, 0xff ;
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out porta, i ;
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LDI i, 0x00 ;
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out ddra, i ;
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; port B pins
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LDI i, 0xff ;
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out portb, i ;
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LDI i, 0x00 ;
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out ddrb, i ;
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; port C pins
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ldi i, 0xff ;
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out portc, i ;
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LDI i, 0x00 ;
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out ddrc, i ;
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; port D pins
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ldi i, 0xff ;
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out portd, i ;
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LDI i, 0x00 ;
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out ddrd, i ;
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;******************************************************************************
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; Init other CPU I/O registers
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;******************************************************************************
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ldi i, 0x80
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out ACSR, i ; turn off comparator
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ldi i, 0x40 ; set stack pointer to top of SRAM
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out SPH, i ;
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ldi i, 0xff ;
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out SPL, i ;
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;******************************************************************************
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; Init RS-232 port
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;******************************************************************************
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InitRS232:
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; set baud rate
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ldi i, 0x0C ;
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; 16MHZ 20MHZ 24MHz
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ldi j, 0x00 ; 115200 xxxx 000A 000C
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sts UBRR0H, j ; 19200 0033 0040 004D
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sts UBRR0L, i ; 9600 0067 0081 009B
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; 4800 00CF 0103 0137
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; ; 2400 019F 0208 0270
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; Enable receiver and transmitter
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ldi i, (1<<RXEN0)|(1<<TXEN0)
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sts UCSR0B, i
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; Set frame format: 8data, 1stop bit
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ldi i, (3<<UCSZ00)
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sts UCSR0C, i
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;******************************************************************************
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; Init program registers
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;******************************************************************************
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clr zero
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ldi i, 0x01
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mov one, i
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ldi i, 0x3F ; IO Page
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mov mmap, i
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;******************************************************************************
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; Show Engine version
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;******************************************************************************
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ldi zl, low(version*2)
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ldi zh, high(version*2)
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out rampz, one
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ver1:
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elpm i, Z+
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tst i
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breq Ready
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call Put_Chr
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rjmp ver1
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;******************************************************************************
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; Main Loop
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;******************************************************************************
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Ready:
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out rampz, zero
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call CPU_RESET
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jmp Main ; Enter CPU Execute Loop
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;***********************
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; Version #
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;***********************
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version: .db 0x0d,0x0a,"Version 3.1 - Starting Emulator... ", 0x0d, 0x0a, 0x00
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;******************************************************************************
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; include CPU emulator and bootloader files (after ROM image)
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;******************************************************************************
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; these files in the application area
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.include "cpu.asm"
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; These files are in the Bootloader section
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.include "bootload.asm"
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.include "xmodem-receive.asm"
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;
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; $0000-$3EFF - 15.75k RAM
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; $3F00-$3FFF - I/O
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; $4000-$FFFF - 48k ROM
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;
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; Version 2.7 supports AVR interrupts and the full AVR IO page access
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; FULL WDC 65C02 instruction set, including BCD mode
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; V 3.0 changed opcode excution to a macro and added a table for IO execute
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; also moved IRQ flag from GPIOR0 ro R5 - EEPROM flag moved to GPIOR0
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; fixed NOP byte count for unused opcoded
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; updated bootloader to load engine across the $8000 word boundary
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; Version 3.1 - corrected opcode behavior
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