138 lines
3.3 KiB
Plaintext
138 lines
3.3 KiB
Plaintext
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DLsim Logic Circuit Analysis (Version 3.02)
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Copyright (c) 1990 CADsim Technologies. All rights reserved.
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Memory = 305640
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Signals = 43 Externals = 16 Elements = 45
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Probes = 6 Buses = 2 Macros = 1
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Sim length = 1399 Step time = 1 Samples = 99
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$ 3bitcom
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A C A N A L Y S I S
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C%%LEG
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OSSTQT
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MEE
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PTT
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AAB
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R
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E
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TIME
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0 100ZZZ
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2 100010
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20 000010
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22 000000
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40 176000
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42 176001
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60 076001
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62 076000
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80 134000
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82 134100
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100 034100
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102 034000
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120 100000
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122 100010
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140 101010
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142 101100
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160 102100
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180 103100
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200 104100
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220 105100
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240 106100
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260 107100
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280 110100
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282 110001
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300 111001
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302 111010
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320 112010
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322 112100
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340 113100
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360 114100
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380 115100
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400 116100
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420 117100
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440 120100
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442 120001
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460 121001
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480 122001
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482 122010
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500 123010
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502 123100
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520 124100
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540 125100
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560 126100
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580 127100
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600 130100
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602 130001
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620 131001
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640 132001
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660 133001
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662 133010
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680 134010
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682 134100
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700 135100
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720 136100
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740 137100
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760 140100
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762 140001
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780 141001
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800 142001
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820 143001
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840 144001
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842 144010
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860 145010
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862 145100
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880 146100
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900 147100
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920 150100
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922 150001
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940 151001
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960 152001
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980 153001
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1000 154001
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1020 155001
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1022 155010
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1040 156010
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1042 156100
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1060 157100
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1080 160100
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1082 160001
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1100 161001
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1120 162001
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1140 163001
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1160 164001
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1180 165001
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1200 166001
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1202 166010
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1220 167010
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1222 167100
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1240 170100
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1242 170001
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1260 171001
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1280 172001
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1300 173001
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1320 174001
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1340 175001
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1360 176001
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1380 177001
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1382 177010
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1399 177010
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Simulation Completed Normally.
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