145 lines
5.4 KiB
Plaintext
145 lines
5.4 KiB
Plaintext
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OPL2PLA - OPAL design entry compiler V016
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Copyright (c) National Semiconductor Corporation 1991,1992
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Input Pins
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==========
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Pin name pin number arch visible default
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-------- ---------- ---- ------- -------
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a0 3 com visible
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a1 2 com visible
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a2 1 com visible
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compare 5 com visible
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b2 7 com visible
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b1 8 com visible
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b0 9 com visible
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Output Pins
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===========
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Pin name pin number arch visible default
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-------- ---------- ---- ------- -------
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lt 13 com visible rst
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eq 15 com visible rst
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gt 17 com visible rst
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set notations
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=============
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seta = [a2,a1,a0]
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setb = [b2,b1,b0]
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EQN2JED - Boolean Equations to JEDEC file assembler (Version V059)
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Copyright (c) National Semiconductor Corporation 1990,1991
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Document file for 3bitcom.eqn
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Device: 16V8
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Pin Label Type
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--- ----- ----
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1 a2 pos,com input
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2 a1 pos,com input
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3 a0 pos,com input
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5 compare pos,com input
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7 b2 pos,com input
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8 b1 pos,com input
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9 b0 pos,com input
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13 lt pos,com output
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15 eq pos,com output
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17 gt pos,com output
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EQN2JED - Boolean Equations to JEDEC file assembler (Version V059)
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Copyright (c) National Semiconductor Corporation 1990,1991
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Device Utilization:
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No of dedicated inputs used : 7/10 (70.0%)
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No of dedicated outputs used : 2/2 (100.0%)
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No of feedbacks used as dedicated outputs : 1/6 (16.7%)
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------------------------------------------
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Pin Label Terms Usage
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------------------------------------------
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17 gt 7/8 (87.5%)
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15 eq 8/8 (100.0%)
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13 lt 7/8 (87.5%)
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------------------------------------------
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Total Terms 22/64 (34.4%)
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------------------------------------------
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EQN2JED - Boolean Equations to JEDEC file assembler (Version V059)
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Copyright (c) National Semiconductor Corporation 1990,1991
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Chip diagram (DIP)
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._____ _____.
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a2 | 1 20 | VCC
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a1 | 2 19 |
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a0 | 3 18 |
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| 4 17 | gt
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compare | 5 16 |
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| 6 15 | eq
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b2 | 7 14 |
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b1 | 8 13 | lt
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b0 | 9 12 |
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GND | 10 11 |
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|______________|
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EQN2JED - Boolean Equations to JEDEC file assembler (Version V059)
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Copyright (c) National Semiconductor Corporation 1990,1991
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Document file for 3bitcom.eqn
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Device: 16V8
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Pin Label Type
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--- ----- ----
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1 a2 pos,com input
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2 a1 pos,com input
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3 a0 pos,com input
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5 compare pos,com input
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7 b2 pos,com input
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8 b1 pos,com input
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9 b0 pos,com input
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13 lt pos,com output
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15 eq pos,com output
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17 gt pos,com output
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EQN2JED - Boolean Equations to JEDEC file assembler (Version V059)
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Copyright (c) National Semiconductor Corporation 1990,1991
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Device Utilization:
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No of dedicated inputs used : 7/10 (70.0%)
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No of dedicated outputs used : 2/2 (100.0%)
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No of feedbacks used as dedicated outputs : 1/6 (16.7%)
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------------------------------------------
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Pin Label Terms Usage
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------------------------------------------
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17 gt 7/8 (87.5%)
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15 eq 8/8 (100.0%)
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13 lt 7/8 (87.5%)
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------------------------------------------
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Total Terms 22/64 (34.4%)
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------------------------------------------
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EQN2JED - Boolean Equations to JEDEC file assembler (Version V059)
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Copyright (c) National Semiconductor Corporation 1990,1991
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Chip diagram (DIP)
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._____ _____.
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a2 | 1 20 | VCC
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a1 | 2 19 |
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a0 | 3 18 |
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| 4 17 | gt
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compare | 5 16 |
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| 6 15 | eq
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b2 | 7 14 |
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b1 | 8 13 | lt
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b0 | 9 12 |
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GND | 10 11 |
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|______________|
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