" *************************************************************** " ZX81VID.ABL " ZX81 ULA replacement " ==================== " " 10/25/97 Bodo Wenzel V1.0, creation " 07/11/97 Bodo Wenzel V1.1, correct ZX80 mode " *************************************************************** module zx81vid title 'ZX81 ULA replacement' " The device and pin definitions are in the file ZX81VID.PIN declarations " === pins and nodes ============================================ " Some of the internal nodes are used for reducing logic (RL), " others because of the destination technology (DT). clock pin; " input n_phi pin istype 'reg'; a15, a14 pin; " input a8, a7, a6, a5, a4, a3, a2, a1, a0 pin istype 'reg'; qa8, qa7, qa6, qa5, qa4, qa3, qa2, qa1, qa0 node istype 'reg'; " DT d7, d6, d5, d4, d3, d2, d1, d0 pin istype 'com'; dd7, dd6, dd5, dd4, dd3, dd2, dd1, dd0 node istype 'com'; " DT n_rd, n_wr, n_iorq, n_mreq, n_m1 pin; " input n_romcs, n_ramcs pin istype 'com'; n_nmi pin istype 'com'; n_halt pin; " input v_tp_o pin istype 'com'; tape_i pin; " input usa_uk pin; " input kbd4, kbd3, kbd2, kbd1, kbd0 pin; " input io_wr_1 node istype 'com'; " RL hsync, vsync, nmi node istype 'com'; db_oe node istype 'com'; " DT h_cnt8, h_cnt7, h_cnt6, h_cnt5, h_cnt4, h_cnt3, h_cnt2, h_cnt1, h_cnt0 node istype 'reg'; h_cnt_res node istype 'com'; " RL row_cnt node istype 'com'; " RL v_tp_o_oe node istype 'com'; " DT fake node istype 'com'; chr_pix7, chr_pix6, chr_pix5, chr_pix4, chr_pix3, chr_pix2, chr_pix1, chr_pix0 node istype 'reg'; chr_pix_load node istype 'com'; " RL chr_inv node istype 'reg'; chr_aen node istype 'reg'; " === constants ================================================= H_CNT_SET = [0,0,0,0,0,0,0,0,0]; " necessary for casting HSYNC_BEGIN = (H_CNT_SET+384); HSYNC_GAP = (H_CNT_SET+32); H_CNT_MAX = (H_CNT_SET+413); " === other declarations ======================================== ddb_4_0 = [dd4..dd0]; ddb = [dd7..dd0]; db_4_0 = [d4..d0]; db_5_0 = [d5..d0]; db = [d7..d0]; kb = [kbd4..kbd0]; h_cnt = [h_cnt8..h_cnt0]; chr_code = [qa8..qa3]; chr_row = [qa2..qa0]; ab = [a8..a0]; ab_code = [a8..a3]; ab_row = [a2..a0]; chr_pix = [chr_pix7..chr_pix0]; x = .x.; c = .c.; k = .k.; z = .z.; x6 = [x, x, x, x, x, x]; x8 = [x, x, x, x, x, x, x, x]; k5 = [k, k, k, k, k]; z3 = [z, z, z]; z6 = [z, z, z, z, z, z]; z8 = [z, z, z, z, z, z, z, z]; " === equations ================================================= equations " --- clock divider --------------------------------------------- " Divides the clock by 2 producing the cpu clock. n_phi.clk = clock; n_phi := !n_phi; " --- memory selects -------------------------------------------- " ROM is selected if cpu accesses adress range 00000H to 03FFFH, " else RAM. when !a15 & !a14 then !n_romcs = !n_mreq; else !n_ramcs = !n_mreq; " --- io ports -------------------------------------------------- " Two latches are used to control the video logic. " Together with the keyboard scan lines the tape input and the " jumper for the vsync frequency is sampled. " If the cpu is to be faked with NOP zeroes are output. io_wr_1 = !n_iorq & !n_wr & !a1; vsync = (!n_iorq & !n_rd & !a0 & !nmi) # (vsync & !(!n_iorq & !n_wr)); nmi = (!n_iorq & !n_wr & !a0) # (nmi & !io_wr_1); dd7 = tape_i & !n_iorq; dd6 = usa_uk & !n_iorq; dd5 = 0 & !n_iorq; ddb_4_0 = kb & !n_iorq; db_oe = chr_aen & !n_m1 # (!n_iorq & !n_rd & !a0); db.oe = db_oe; " The equations of the nodes and pins have to be equal! DT d7 = tape_i & !n_iorq; d6 = usa_uk & !n_iorq; d5 = 0 & !n_iorq; db_4_0 = kb & !n_iorq; " --- video ----------------------------------------------------- " The h_cnt divides the clock by 414 generating the signal n_nmi " (if enabled) and hsync. Both signals may glitch! " If the cpu activates vsync the h_cnt is reset synchronously. " In ZX80 mode (and for using ASZMIC) the h_cnt is set by INTACK " (iorq and m1) synchronously to the end of line. " At the output v_tp_o should be a resistor ladder to produce the " correct levels (0=sync, z=black, 1=white). " The shift register is loaded if pattern data are ready " otherwise it is shifted. h_cnt.clk = clock; when !n_iorq & !n_m1 then h_cnt := HSYNC_BEGIN-HSYNC_GAP; else h_cnt := (h_cnt+1) & !h_cnt_res; h_cnt_res = (h_cnt==H_CNT_MAX) # vsync; hsync = h_cnt>=HSYNC_BEGIN; n_nmi = !(nmi & hsync); v_tp_o_oe = vsync # hsync # (chr_pix7==0); v_tp_o.oe = v_tp_o_oe; when vsync # hsync then v_tp_o = 0; else v_tp_o = 1; chr_pix_load = chr_aen & !n_mreq & n_m1 & !n_phi; chr_pix.clk = clock; when chr_pix_load then chr_pix := db $ chr_inv; else chr_pix := [chr_pix6..chr_pix0, 0]; " --- character generator --------------------------------------- " Faking the cpu is done if an opcode fetch at addresses " >= 08000H appears without halted cpu or D6=1. " If a character pattern is to be loaded the signal chr_aen is " activated. It will enable the output of the pattern address. " The flipflops for character inversion and code are loaded one " clock after raising fake. " The row counter is synchronously reset by vsync and is " incremented at the end of every line. fake = !n_phi & !n_mreq & !n_m1 & a15 & n_halt & !d6; chr_aen.clk = clock; chr_aen := fake # (chr_aen & (n_phi # n_mreq)); chr_inv.clk = clock; when fake then chr_inv := d7; else chr_inv := chr_inv; chr_code.clk = clock; when fake then chr_code := db_5_0; else chr_code := chr_code; row_cnt = (h_cnt==HSYNC_BEGIN); chr_row.clk = clock; when row_cnt then chr_row := (chr_row+1) & !vsync; else chr_row := chr_row & !vsync; ab.oe = chr_aen & n_m1; " The equations of the pins and nodes have to be equal! DT ab.clk = clock; when fake then ab_code := db_5_0; else ab_code := chr_code; when row_cnt then ab_row := (chr_row+1) & !vsync; else ab_row := chr_row & !vsync; " === test vectors ============================================== " They probably have to be edited every time changes in the " equations are made! " --- clock divider --------------------------------------------- test_vectors 'clock divider' ([clock] -> [n_phi]) @repeat 10 { [c ] -> [x ]; } " --- memory selects -------------------------------------------- test_vectors 'memory selects' ([n_mreq, a15, a14] -> [n_romcs, n_ramcs]) [1 , 0 , 0 ] -> [1 , 1 ]; [1 , 0 , 1 ] -> [1 , 1 ]; [1 , 1 , 0 ] -> [1 , 1 ]; [1 , 1 , 1 ] -> [1 , 1 ]; [0 , 0 , 0 ] -> [0 , 1 ]; [1 , 0 , 0 ] -> [1 , 1 ]; [0 , 0 , 1 ] -> [1 , 0 ]; [1 , 0 , 1 ] -> [1 , 1 ]; [0 , 1 , 0 ] -> [1 , 0 ]; [1 , 1 , 0 ] -> [1 , 1 ]; [0 , 1 , 1 ] -> [1 , 0 ]; [1 , 1 , 1 ] -> [1 , 1 ]; " --- io ports -------------------------------------------------- test_vectors 'video control latches' ([n_iorq, n_rd, n_wr, a1, a0] -> [vsync, nmi]) [0 , 1 , 0 , 0 , 1 ] -> [0 , 0 ]; [1 , k , k , k , k ] -> [0 , 0 ]; [k , 1 , 1 , k , k ] -> [0 , 0 ]; [0 , 0 , 1 , 0 , 0 ] -> [1 , 0 ]; [1 , k , k , k , k ] -> [1 , 0 ]; [0 , 1 , 0 , 1 , 1 ] -> [0 , 0 ]; [1 , k , k , k , k ] -> [0 , 0 ]; [0 , 0 , 1 , 1 , 0 ] -> [1 , 0 ]; [1 , k , k , k , k ] -> [1 , 0 ]; [0 , 1 , 0 , 1 , 1 ] -> [0 , 0 ]; [1 , k , k , k , k ] -> [0 , 0 ]; [0 , 1 , 0 , 1 , 0 ] -> [0 , 1 ]; [1 , k , k , k , k ] -> [0 , 1 ]; [0 , 0 , 1 , 1 , 0 ] -> [0 , 1 ]; [1 , k , k , k , k ] -> [0 , 1 ]; [0 , 1 , 0 , 0 , 1 ] -> [0 , 0 ]; test_vectors 'keyboard etc. input' ([n_iorq, n_rd, a0, tape_i, usa_uk, kb ] -> [db ]) [1 , k , k , k , k , k5 ] -> [z8 ]; [k , 1 , k , k , k , k5 ] -> [z8 ]; [k , k , 1 , k , k , k5 ] -> [z8 ]; [0 , 0 , 0 , 0 , 0 , ^b11110] -> [^h1E]; [1 , k , k , k , k , k5 ] -> [z8 ]; [0 , 0 , 0 , 1 , 0 , ^b11101] -> [^h9D]; [1 , k , k , k , k , k5 ] -> [z8 ]; [0 , 0 , 0 , 0 , 1 , ^b11011] -> [^h5B]; [1 , k , k , k , k , k5 ] -> [z8 ]; [0 , 0 , 0 , 1 , 1 , ^b10111] -> [^hD7]; [1 , k , k , k , k , k5 ] -> [z8 ]; [0 , 0 , 0 , 0 , 1 , ^b01111] -> [^h4F]; [1 , k , k , k , k , k5 ] -> [z8 ]; [0 , 0 , 0 , 1 , 0 , ^b10101] -> [^h95]; [1 , k , k , k , k , k5 ] -> [z8 ]; [0 , 0 , 0 , 0 , 0 , ^b01010] -> [^h0A]; [1 , k , k , k , k , k5 ] -> [z8 ]; " --- video ----------------------------------------------------- test_vectors 'sync and nmi' ([clock, n_m1, n_iorq, n_rd, n_wr, a1, a0] -> [h_cnt, v_tp_o, n_nmi]) " clk m1 iorq rd wr a1 a0 -> h_cnt v_tp_o nmi [c , 1, 0 , 0, 1, k, 0] -> [ x , 0 , 1 ]; [0 , 1, 0 , 1, 0, 1, 0] -> [ 0 , 1 , 1 ]; @repeat 382 { [c , 1, 1 , x, x, x, x] -> [ x , 1 , 1 ]; } [c , 1, 1 , x, x, x, x] -> [383 , 1 , 1 ]; [c , 1, 1 , x, x, x, x] -> [384 , 0 , 0 ]; @repeat 20 { [c , 1, 1 , x, x, x, x] -> [ x , 0 , 0 ]; } [0 , 1, 0 , 1, 0, 0, 1] -> [404 , 0 , 1 ]; @repeat 8 { [c , 1, 1 , x, x, x, x] -> [ x , 0 , 1 ]; } [c , 1, 1 , x, x, x, x] -> [413 , 0 , 1 ]; [c , 1, 1 , x, x, x, x] -> [ 0 , 1 , 1 ]; " clk m1 iorq rd wr a1 a0 -> h_cnt v_tp_o nmi @repeat 12 { [c , 1, 1 , x, x, x, x] -> [ x , 1 , 1 ]; } [c , 1, 1 , x, x, x, x] -> [ 13 , 1 , 1 ]; [c , 0, 0 , x, x, x, x] -> [352 , 1 , 1 ]; [c , 0, 0 , x, x, x, x] -> [352 , 1 , 1 ]; [c , 0, 0 , x, x, x, x] -> [352 , 1 , 1 ]; @repeat 31 { [c , 1, 1 , x, x, x, x] -> [ x , 1 , 1 ]; } @repeat 29 { [c , 1, 1 , x, x, x, x] -> [ x , 0 , 1 ]; } [c , 1, 1 , x, x, x, x] -> [413 , 0 , 1 ]; [c , 1, 1 , x, x, x, x] -> [ 0 , 1 , 1 ]; " The video output is tested with the character generator... " --- character generator --------------------------------------- test_vectors 'fake signal' ([clock, n_iorq, n_mreq, n_m1, a15, n_halt, d6] -> [n_phi, fake]) " if the check fails on n_phi, un/comment the following line " [c , 1 , 1 , x , x , x , x ] -> [1 , 0 ]; [c , 1 , 1 , x , x , x , x ] -> [0 , 0 ]; [0 , 1 , 1 , 0 , 1 , 1 , 0 ] -> [0 , 0 ]; [0 , 1 , 0 , 1 , 1 , 1 , 0 ] -> [0 , 0 ]; [0 , 1 , 0 , 0 , 0 , 1 , 0 ] -> [0 , 0 ]; [0 , 1 , 0 , 0 , 1 , 0 , 0 ] -> [0 , 0 ]; [0 , 1 , 0 , 0 , 1 , 1 , 1 ] -> [0 , 0 ]; [c , 1 , 1 , x , x , x , x ] -> [1 , 0 ]; [0 , 1 , 0 , 0 , 1 , 1 , 0 ] -> [1 , 0 ]; [c , 1 , 0 , 0 , 1 , 1 , 0 ] -> [0 , 1 ]; test_vectors 'catch character code' ([clock, n_iorq, n_mreq, n_m1, a15, n_halt, db] -> [n_phi, db, chr_inv, ab_code, chr_aen, chr_pix]) " clk io mrq m1 a15 hlt db -> phi db inv code aen pix [c , 1, 1 , 1, x , x , z8 ] -> [1 , x8 , x , z6 , x , x8 ]; [c , 1, 0 , 1, x , x , x8 ] -> [0 , x8 , x , x6 , x , x8 ]; [c , 1, 0 , 1, x , x , x8 ] -> [1 , x8 , x , x6 , 0 , x8 ]; [c , 1, 1 , 1, x , x , z8 ] -> [0 , x8 , x , z6 , 0 , x8 ]; [c , 1, 1 , 0, 1 , 1 , z8 ] -> [1 , z8 , x , z6 , 0 , x8 ]; [c , 1, 0 , 0, 1 , 1 , x8 ] -> [0 , z8 , x , z6 , 0 , x8 ]; [c , 1, 0 , 0, 1 , 1 , ^h15] -> [1 , ^h00, 0 , z6 , 1 , x8 ]; [c , 1, 0 , 0, 1 , 1 , z8 ] -> [0 , ^h00, 0 , z6 , 1 , x8 ]; [0 , 1, 1 , 1, x , 1 , z8 ] -> [0 , z8 , 0 , ^h15, 1 , x8 ]; [c , 1, 1 , 1, x , 1 , z8 ] -> [1 , z8 , 0 , ^h15, 1 , x8 ]; [c , 1, 0 , 1, x , 1 , x8 ] -> [0 , z8 , 0 , ^h15, 1 , x8 ]; [c , 1, 0 , 1, x , 1 , ^h3C] -> [1 , z8 , 0 , z6 , 0 , ^h3C]; [c , 1, 1 , 1, x , 1 , z8 ] -> [0 , z8 , 0 , z6 , 0 , ^h78]; " clk io mrq m1 a15 hlt db -> phi db inv code aen pix [c , 1, 1 , 0, 1 , 1 , z8 ] -> [1 , z8 , 0 , z6 , 0 , ^hF0]; [c , 1, 0 , 0, 1 , 1 , x8 ] -> [0 , z8 , 0 , z6 , 0 , ^hE0]; [c , 1, 0 , 0, 1 , 1 , ^hAA] -> [1 , ^h00, 1 , z6 , 1 , ^hC0]; [c , 1, 0 , 0, 1 , 1 , z8 ] -> [0 , ^h00, 1 , z6 , 1 , ^h80]; [0 , 1, 1 , 1, x , 1 , z8 ] -> [0 , z8 , 1 , ^h2A, 1 , ^h80]; [c , 1, 1 , 1, x , 1 , z8 ] -> [1 , z8 , 1 , ^h2A, 1 , ^h00]; [c , 1, 0 , 1, x , 1 , x8 ] -> [0 , z8 , 1 , ^h2A, 1 , ^h00]; [c , 1, 0 , 1, x , 1 , ^h5A] -> [1 , z8 , 1 , z6 , 0 , ^hA5]; [c , 1, 1 , 1, x , 1 , z8 ] -> [0 , z8 , 1 , z6 , 0 , ^h4A]; [c , 1, 1 , 0, 1 , 1 , z8 ] -> [1 , z8 , 1 , z6 , 0 , ^h94]; [c , 1, 0 , 0, 1 , 1 , x8 ] -> [0 , z8 , 1 , z6 , 0 , ^h28]; [c , 1, 0 , 0, 1 , 1 , ^h76] -> [1 , z8 , x , z6 , 0 , ^h50]; [c , 1, 0 , 0, 1 , 1 , z8 ] -> [0 , z8 , x , z6 , 0 , ^hA0]; [0 , 1, 1 , 1, x , 1 , z8 ] -> [0 , z8 , x , z6 , 0 , ^hA0]; [c , 1, 1 , 1, x , 1 , z8 ] -> [1 , z8 , x , z6 , 0 , ^h40]; [c , 1, 0 , 1, x , 1 , x8 ] -> [0 , z8 , x , z6 , 0 , ^h80]; [c , 1, 0 , 1, x , 1 , x8 ] -> [1 , z8 , x , z6 , 0 , ^h00]; [c , 1, 1 , 1, x , 1 , z8 ] -> [0 , z8 , x , z6 , 0 , ^h00]; " clk io mrq m1 a15 hlt db -> phi db inv code aen pix [c , 1, 1 , 0, 1 , 1 , z8 ] -> [1 , z8 , x , z6 , 0 , ^h00]; [c , 1, 0 , 0, 1 , 1 , x8 ] -> [0 , z8 , x , z6 , 0 , ^h00]; [c , 1, 0 , 0, 1 , 1 , ^h96] -> [1 , ^h00, 1 , z6 , 1 , ^h00]; [c , 1, 0 , 0, 1 , 1 , z8 ] -> [0 , ^h00, 1 , z6 , 1 , ^h00]; [0 , 1, 1 , 1, x , 1 , z8 ] -> [0 , z8 , 1 , ^h16, 1 , ^h00]; [c , 1, 1 , 1, x , 1 , z8 ] -> [1 , z8 , 1 , ^h16, 1 , ^h00]; [c , 1, 0 , 1, x , 1 , x8 ] -> [0 , z8 , 1 , ^h16, 1 , ^h00]; [c , 1, 0 , 1, x , 1 , ^hC3] -> [1 , z8 , 1 , z6 , 0 , ^h3C]; [c , 1, 1 , 1, x , 1 , z8 ] -> [0 , z8 , 1 , z6 , 0 , ^h78]; [c , 1, 1 , 0, 0 , 1 , z8 ] -> [1 , z8 , 1 , z6 , 0 , ^hF0]; [c , 1, 0 , 0, 0 , 1 , x8 ] -> [0 , z8 , 1 , z6 , 0 , ^hE0]; [c , 1, 0 , 0, 0 , 1 , x8 ] -> [1 , z8 , x , z6 , 0 , ^hC0]; [c , 1, 0 , 0, 0 , 1 , z8 ] -> [0 , z8 , x , z6 , 0 , ^h80]; [0 , 1, 1 , 1, x , 1 , z8 ] -> [0 , z8 , x , z6 , 0 , ^h80]; [c , 1, 1 , 1, x , 1 , z8 ] -> [1 , z8 , x , z6 , 0 , ^h00]; [c , 1, 0 , 1, x , 1 , x8 ] -> [0 , z8 , x , z6 , 0 , ^h00]; [c , 1, 0 , 1, x , 1 , x8 ] -> [1 , z8 , x , z6 , 0 , ^h00]; [c , 1, 1 , 1, x , 1 , z8 ] -> [0 , z8 , x , z6 , 0 , ^h00]; test_vectors 'combined video output' ([clock, n_iorq, n_mreq, n_m1, a15, n_halt, db ] -> [n_phi, v_tp_o]) " clk io mrq m1 a15 halt db -> phi, v_tp_o [c , 1, 1 , 0, 1 , 1 , z8 ] -> [1 , 1 ]; [c , 1, 0 , 0, 1 , 1 , x8 ] -> [0 , 1 ]; [c , 1, 0 , 0, 1 , 1 , ^hAA] -> [1 , 1 ]; [c , 1, 0 , 0, 1 , 1 , z8 ] -> [0 , 1 ]; [c , 1, 1 , 1, x , 1 , z8 ] -> [1 , 1 ]; [c , 1, 0 , 1, x , 1 , x8 ] -> [0 , 1 ]; [c , 1, 0 , 1, x , 1 , ^h5A] -> [1 , z ]; [c , 1, 1 , 1, x , 1 , z8 ] -> [0 , 1 ]; [c , 1, 1 , 0, 1 , 1 , z8 ] -> [1 , z ]; [c , 1, 0 , 0, 1 , 1 , x8 ] -> [0 , 1 ]; [c , 1, 0 , 0, 1 , 1 , ^h76] -> [1 , 1 ]; [c , 1, 0 , 0, 1 , 1 , z8 ] -> [0 , z ]; [c , 1, 1 , 1, x , 1 , z8 ] -> [1 , 1 ]; [c , 1, 0 , 1, x , 1 , x8 ] -> [0 , z ]; [c , 1, 0 , 1, x , 1 , x8 ] -> [1 , 1 ]; [c , 1, 1 , 1, x , 1 , z8 ] -> [0 , 1 ]; test_vectors 'row counter' ([clock, n_mreq, n_m1, n_iorq, n_rd, n_wr, a15, a1, a0, n_halt, db] -> [n_phi, h_cnt, ab_row]) " clk mrq m1 iorq rd wr a15 a1 a0 hlt db -> ph cnt row [c , 1 , 1, 0 , 0, 1, x , 1, 0, x , x8 ] -> [1, 0 , z3 ]; [c , 1 , 1, 0 , 1, 0, x , 1, 1, x , x8 ] -> [0, 1 , z3 ]; @repeat 187 { [c , 1 , x, 1 , x, x, x , x, x, x , x8 ] -> [1, x , z3 ]; [c , 1 , x, 1 , x, x, x , x, x, x , x8 ] -> [0, x , z3 ]; } @const row=0; @repeat 7 { " clk mrq m1 iorq rd wr a15 a1 a0 hlt db -> ph cnt row [c , 1 , 0, 1 , x, x, 1 , x, x, 1 , z8 ] -> [1, 376, z3 ]; [c , 0 , 0, 1 , x, x, 1 , x, x, 1 , x8 ] -> [0, 377, z3 ]; [c , 0 , 0, 1 , x, x, 1 , x, x, 1 , ^h99] -> [1, 378, z3 ]; [c , 0 , 0, 1 , x, x, 1 , x, x, 1 , z8 ] -> [0, 379, z3 ]; [0 , 1 , 1, 1 , x, x, x , x, x, 1 , z8 ] -> [0, 379, row]; [c , 1 , 1, 1 , x, x, x , x, x, 1 , z8 ] -> [1, 380, row]; [c , 0 , 1, 1 , x, x, x , x, x, 1 , x8 ] -> [0, 381, row]; [c , 0 , 1, 1 , x, x, x , x, x, 1 , x8 ] -> [1, 382, z3 ]; [c , 1 , 1, 1 , x, x, x , x, x, 1 , z8 ] -> [0, 383, z3 ]; @const row=row+1; [c , 1 , 0, 1 , x, x, 1 , x, x, 1 , z8 ] -> [1, 384, z3 ]; [c , 0 , 0, 1 , x, x, 1 , x, x, 1 , x8 ] -> [0, 385, z3 ]; [c , 0 , 0, 1 , x, x, 1 , x, x, 1 , ^h99] -> [1, 386, z3 ]; [c , 0 , 0, 1 , x, x, 1 , x, x, 1 , z8 ] -> [0, 387, z3 ]; [0 , 1 , 1, 1 , x, x, x , x, x, 1 , z8 ] -> [0, 387, row]; [c , 1 , 1, 1 , x, x, x , x, x, 1 , z8 ] -> [1, 388, row]; [c , 0 , 1, 1 , x, x, x , x, x, 1 , x8 ] -> [0, 389, row]; [c , 0 , 1, 1 , x, x, x , x, x, 1 , x8 ] -> [1, 390, z3 ]; [c , 1 , 1, 1 , x, x, x , x, x, 1 , z8 ] -> [0, 391, z3 ]; @repeat 199 { [c , 1 , x, 1 , x, x, x , x, x, x , x8 ] -> [1, x , z3 ]; [c , 1 , x, 1 , x, x, x , x, x, x , x8 ] -> [0, x , z3 ]; } } " clk mrq m1 iorq rd wr a15 a1 a0 hlt db -> ph cnt row [c , 1 , x, 1 , x, x, x , x, x, x , x8 ] -> [1, 376, z3 ]; [c , 1 , x, 1 , x, x, x , x, x, x , x8 ] -> [0, 377, z3 ]; [c , 1 , x, 1 , x, x, x , x, x, x , x8 ] -> [1, 378, z3 ]; [c , 1 , x, 1 , x, x, x , x, x, x , x8 ] -> [0, 379, z3 ]; [c , 1 , 0, 1 , x, x, 1 , x, x, 1 , z8 ] -> [1, 380, z3 ]; [c , 0 , 0, 1 , x, x, 1 , x, x, 1 , x8 ] -> [0, 381, z3 ]; [c , 0 , 0, 1 , x, x, 1 , x, x, 1 , ^h99] -> [1, 382, z3 ]; [c , 0 , 0, 1 , x, x, 1 , x, x, 1 , z8 ] -> [0, 383, z3 ]; [0 , 1 , 1, 1 , x, x, x , x, x, 1 , z8 ] -> [0, 383, 7 ]; [c , 1 , 1, 1 , x, x, x , x, x, 1 , z8 ] -> [1, 384, 7 ]; [c , 0 , 1, 1 , x, x, x , x, x, 1 , x8 ] -> [0, 385, 0 ]; [c , 0 , 1, 1 , x, x, x , x, x, 1 , x8 ] -> [1, 386, z3 ]; [c , 1 , 1, 1 , x, x, x , x, x, 1 , z8 ] -> [0, 387, z3 ]; " === end ======================================================= end