daily_automated

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paolo.iocco
2023-03-13 08:36:51 +00:00
parent 5347889cd2
commit f29dcc4188
5439 changed files with 1065799 additions and 0 deletions

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*******************************************************************************
Z80_Dec
*******************************************************************************
CUPL(WM) 5.0a Serial# 60008009
Device g16v8s Library DLIB-h-40-9
Created Tue Apr 25 11:46:07 2017
Name Z80_Dec
Partno g16v8
Revision 00
Date 25/04/17
Designer Paolo Iocco
Company GC73
Assembly 00
Location Munich
===============================================================================
Expanded Product Terms
===============================================================================
!EPROM =>
!A13 & !A14 & !A15 & !MREQ
!IO0 =>
!A6 & !A7 & !IOREQ
!IO1 =>
A6 & !A7 & !IOREQ
!RAM =>
A13 & !A14 & !A15 & !MREQ
===============================================================================
Symbol Table
===============================================================================
Pin Variable Pterms Max Min
Pol Name Ext Pin Type Used Pterms Level
--- -------- --- --- ---- ------ ------ -----
A6 6 V - - -
A7 5 V - - -
A13 4 V - - -
A14 3 V - - -
A15 2 V - - -
EPROM 19 V 1 8 1
IO0 17 V 1 8 1
IO1 16 V 1 8 1
! IOREQ 8 V - - -
! MREQ 7 V - - -
RAM 18 V 1 8 1
LEGEND D : default variable F : field G : group
I : intermediate variable N : node M : extended node
U : undefined V : variable X : extended variable
T : function

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{COMPONENT H:\WORKSPACE\01_CUPL\Z80_DECODER\Z80_DEC.SYM
{ENVIRONMENT
{PDIFvrev 3.00}
{Program "CUPL(WM) Version 5.0a"}
{DBtype "Schematic"}
{DBvrev 1.01}
{DBtime "Mon Dec 07 23:08:19 2020 "}
{DBunit "MIL"}
{DBgrid 10}
{Lyrstr "WIRES" 1 "BUS" 1 "GATE" 2 "IEEE" 2 "PINFUN" 3 "PINNUM" 1
"PINNAM" 6 "PINCON" 4 "REFDES" 2 "ATTR" 6 "SDOT" 1
"DEVICE" 5 "OUTLIN" 5 "ATTR2" 6 "NOTES" 6 "NETNAM" 4
"CMPNAM" 5 "BORDER" 5}
}
{USER
{VIEW
{Mode SYMB}
{Nlst OPEN}
{Vw 0 0 2}
{Lv 12 2 2 2 0 0 2 2 2 2 0 0 2 1 2 0 0 0 0}
{Gs 10 10}
}
}
{DISPLAY
[Ly "PINNUM"]
[Ls "SOLID"][Wd 0]
[Ts 15][Tj "LC"][Tr 0][Tm "N"]
}
{SYMBOL
{PIN_DEF
[Ly "PINCON"]
{P IO1 {Pt "I/O"}{Lq 0}{Ploc 280 20}}
{P IO0 {Pt "I/O"}{Lq 0}{Ploc 280 40}}
{P RAM {Pt "I/O"}{Lq 0}{Ploc 280 60}}
{P EPROM {Pt "I/O"}{Lq 0}{Ploc 280 80}}
}
{PKG
[Ly "REFDES"]
[Ts 25][Tj "CB"][Tr 0][Tm "N"]
{Rdl 190 110}
[Ly "PINNUM"]
[Ts 15][Tj "LC"]
{Pnl 260 30}
{Pnl 260 50}
{Pnl 260 70}
{Pnl 260 90}
{Sd A 16 17 18 19}
}
{PIC
[Ly "GATE"]
[Ts 15][Tj "LC"][Tr 0][Tm "N"]
{R 130 100 250 0}
{L 250 20 280 20}
{L 250 40 280 40}
{L 250 60 280 60}
{L 250 80 280 80}
[Ly "PINNAM"]
[Tj "LC"]
[Tj "RC"]
{T "IO1" 240 20}
{T "IO0" 240 40}
{T "RAM" 240 60}
{T "EPROM" 240 80}
[Ly "DEVICE"]
[Tj "CT"]
{T "VIRTUAL" 190 -10}
}
{ATR
{IN
{Org 100 20}
{Ty 255}
}
{EX
[Ly "ATTR2"]
[Ts 12][Tj "CT"][Tr 0][Tm "N"]
{At PLD H:\WORKSPACE\01_CUPL\Z80_DECODER\Z80_DEC 190 100}
}
}
}
{DETAIL
{ANNOTATE
}
{NET_DEF
{N IO1
}
{N IO0
}
{N RAM
}
{N EPROM
}
}
{SUBCOMP
}
}
}

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Name Z80_Dec;
PartNo g16v8;
Date 25/04/17;
Revision 00;
Designer Paolo Iocco;
Company GC73;
Assembly 00;
Location Munich;
Device G16V8;
ORDER: MREQ, A15, A14, A13, EPROM, RAM, IOREQ, A7, A6, IO0, IO1;
VECTORS:
0000**000**
0001**001**
0010**010**
0011**011**
0100**100**
0101**101**
0110**110**
0111**111**
1000**000**
1001**001**
1010**010**
1011**011**
1100**100**
1101**101**
1110**110**
1111**111**

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CUPL(WM) 5.0a Serial# 60008009
Device g16v8s Library DLIB-h-40-9
Created Tue Apr 25 15:09:40 2017
Name Z80_Dec
Partno g16v8
Revision 00
Date 25/04/17
Designer Paolo Iocco
Company GC73
Assembly 00
Location Munich
*QP20
*QF2194
*QV16
*G0
*F0
*L00000 10111011101111111111011111111111
*L00256 10111011011111111111011111111111
*L00512 11111111111110111011111101111111
*L00768 11111111111110110111111101111111
*L02048 00000000011001110011000100110110
*L02080 01110110001110000000000000000000
*L02112 00000000000011111111111111111111
*L02144 11111111111111111111111111111111
*L02176 111111111111111110
*C1A95
*P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
*V0001 X0000011XNXXXXXHLHLN
*V0002 X0010111XNXXXXXLHLHN
*V0003 X0101011XNXXXXXHHHHN
*V0004 X0111111XNXXXXXHHHHN
*V0005 X1000010XNXXXXXHHHHN
*V0006 X1010110XNXXXXXHHHHN
*V0007 X1101010XNXXXXXHHHHN
*V0008 X1111110XNXXXXXHHHHN
*V0009 X0000001XNXXXXXHLHHN
*V0010 X0010101XNXXXXXLHHHN
*V0011 X0101001XNXXXXXHHHHN
*V0012 X0111101XNXXXXXHHHHN
*V0013 X1000000XNXXXXXHHHHN
*V0014 X1010100XNXXXXXHHHHN
*V0015 X1101000XNXXXXXHHHHN
*V0016 X1111100XNXXXXXHHHHN
*0DE4

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Name Z80_Dec;
Partno g16v8;
Date 25/04/17;
Revision 00;
Designer Paolo Iocco;
Company GC73;
Assembly 00;
Location Munich;
Device G16V8;
/* ****************************** */
/* Z80 memory and I/O decoder */
/* Memory Map */
/* 0000-1FFF EPROM */
/* 2000-3FFF RAM */
/* xxx IO0 */
/* yyy IO1 */
/* ****************************** */
/** Inputs **/
pin 2 = A15;
pin 3 = A14;
pin 4 = A13;
pin 5 = A7;
pin 6 = A6;
pin 7 = !MREQ;
pin 8 = !IOREQ;
/** Outputs **/
pin 19 = EPROM;
pin 18 = RAM;
pin 17 = IO0;
pin 16 = IO1;
/** Logic Equations **/
!EPROM = !A15 & !A14 & !A13 & !MREQ ;
!RAM = !A15 & !A14 & A13 & !MREQ ;
!IO0 = !A7 & !A6 & !IOREQ ;
!IO1 = !A7 & A6 & !IOREQ ;