daily_automated

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paolo.iocco
2023-03-13 08:36:51 +00:00
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*******************************************************************************
6502_DECODER
*******************************************************************************
CUPL(WM) 5.0a Serial# 60008009
Device g22v10 Library DLIB-h-40-1
Created Tue Apr 25 11:59:30 2017
Name 6502_DECODER
Partno Lattice22V10B
Revision 01
Date 02/04/15
Designer shalewyn.com
Company shalewyn.com
Assembly XXXXX
Location XXXXX
===============================================================================
Expanded Product Terms
===============================================================================
BASERAM =>
!A12 & !A13 & !A14 & !A15
RD =>
PHI2 & R_W
ROM =>
A12 & !A14 & A15
# !A12 & A13 & A15
# !A13 & A14 & A15
# A12 & A13 & A14 & A15
SWAPBANK0 =>
A13 & !A15 & !sb0 & !sb1
# !A13 & A14 & !A15 & !sb0 & !sb1
SWAPBANK1 =>
A13 & !A15 & !sb0 & sb1
# !A13 & A14 & !A15 & !sb0 & sb1
SWAPBANK2 =>
A13 & !A15 & sb0 & !sb1
# !A13 & A14 & !A15 & sb0 & !sb1
SWAPBANK3 =>
!A12 & A13 & !A14 & !A15 & !sb0 & sb1
# A12 & A13 & !A15 & sb0 & sb1
# !A13 & A14 & !A15 & sb0 & sb1
# !A12 & A13 & A14 & !A15 & sb0 & sb1
VIA1 =>
!A4 & !A5 & !A12 & !A13 & !A14 & A15
VIA2 =>
A4 & !A5 & !A12 & !A13 & !A14 & A15
WR =>
PHI2 & !R_W
BASERAM.oe =>
1
RD.oe =>
1
ROM.oe =>
1
SWAPBANK0.oe =>
1
SWAPBANK1.oe =>
1
SWAPBANK2.oe =>
1
SWAPBANK3.oe =>
1
VIA1.oe =>
1
VIA2.oe =>
1
WR.oe =>
1
===============================================================================
Symbol Table
===============================================================================
Pin Variable Pterms Max Min
Pol Name Ext Pin Type Used Pterms Level
--- -------- --- --- ---- ------ ------ -----
A4 9 V - - -
A5 8 V - - -
A6 7 V - - -
A12 6 V - - -
A13 5 V - - -
A14 4 V - - -
A15 3 V - - -
! BASERAM 18 V 1 16 1
PHI2 1 V - - -
! RD 14 V 1 8 1
! ROM 23 V 4 8 1
R_W 2 V - - -
! SWAPBANK0 19 V 2 16 1
! SWAPBANK1 20 V 2 14 1
! SWAPBANK2 21 V 2 12 1
! SWAPBANK3 22 V 4 10 1
! VIA1 16 V 1 12 1
! VIA2 17 V 1 14 1
! WR 15 V 1 10 1
sb0 10 V - - -
sb1 11 V - - -
BASERAM oe 18 D 1 1 0
RD oe 14 D 1 1 0
ROM oe 23 D 1 1 0
SWAPBANK0 oe 19 D 1 1 0
SWAPBANK1 oe 20 D 1 1 0
SWAPBANK2 oe 21 D 1 1 0
SWAPBANK3 oe 22 D 1 1 0
VIA1 oe 16 D 1 1 0
VIA2 oe 17 D 1 1 0
WR oe 15 D 1 1 0
LEGEND D : default variable F : field G : group
I : intermediate variable N : node M : extended node
U : undefined V : variable X : extended variable
T : function

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CUPL(WM) 5.0a Serial# MW-10400000
Device g22v10 Library DLIB-h-40-1
Created Tue Sep 14 16:00:25 2021
Name 6502_DECODER
Partno Lattice22V10B
Revision 01
Date 02/04/15
Designer shalewyn.com
Company shalewyn.com
Assembly XXXXX
Location XXXXX
*QP24
*QF5892
*G0
*F0
*L00032 00000000000011111111111111111111
*L00064 11111111111111111111111111111111
*L00096 01111011111101111111111111111111
*L00128 11111111111101111111011110111111
*L00160 11111111111111111111111101110111
*L00192 10111111111111111111111111111111
*L00224 11110111011101110111111111111111
*L00256 11111111000000000000000000000000
*L00416 00000000000000000000000011111111
*L00448 11111111111111111111111111111111
*L00480 11111111111110111011011110111111
*L00512 11111111101101111111111110111111
*L00544 01110111111111111111011101111111
*L00576 11111011011110111111111111111111
*L00608 01110111111111111011011101111011
*L00640 11111111111101110111000000000000
*L00896 00000000000000000000000000001111
*L00928 11111111111111111111111111111111
*L00960 11111111111111111011111101111111
*L00992 11111111111101111011111111111011
*L01024 01111011111111111111111101111011
*L01472 00000000000000000000000011111111
*L01504 11111111111111111111111111111111
*L01536 11111111111110111111011111111111
*L01568 11111111101101111111111110110111
*L01600 10111111111111111111101101110000
*L02144 00000000000011111111111111111111
*L02176 11111111111111111111111111111111
*L02208 10111111011111111111111111111011
*L02240 10111111111110110111101111111111
*L02272 11111111101110110000000000000000
*L02880 00000000000000000000000011111111
*L02912 11111111111111111111111111111111
*L02944 11111111111110111011101110111111
*L02976 11111111111111110000000000000000
*L03648 00001111111111111111111111111111
*L03680 11111111111111111111111101111011
*L03712 10111011111110110111111111110000
*L04288 00000000000000000000000011111111
*L04320 11111111111111111111111111111111
*L04352 11111111111101111011101110111111
*L04384 10111011111111110000000000000000
*L04864 00000000000000000000111111111111
*L04896 11111111111111111111111111111111
*L04928 01111011111111111111111111111111
*L04960 11111111111100000000000000000000
*L05344 00000000000000000000000011111111
*L05376 11111111111111111111111111111111
*L05408 11110111011111111111111111111111
*L05440 11111111111111110000000000000000
*L05792 00000000000000000101010101010101
*L05824 01010100110001100001011101000111
*L05856 01000110100101100011011001010011
*L05888 0010
*CA0D3
*F852

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{COMPONENT E:\0_WORKSPACE\01_CUPL\6502_DECODER.SYM
{ENVIRONMENT
{PDIFvrev 3.00}
{Program "CUPL(WM) Version 5.0a"}
{DBtype "Schematic"}
{DBvrev 1.01}
{DBtime "Tue Apr 25 11:59:30 2017 "}
{DBunit "MIL"}
{DBgrid 10}
{Lyrstr "WIRES" 1 "BUS" 1 "GATE" 2 "IEEE" 2 "PINFUN" 3 "PINNUM" 1
"PINNAM" 6 "PINCON" 4 "REFDES" 2 "ATTR" 6 "SDOT" 1
"DEVICE" 5 "OUTLIN" 5 "ATTR2" 6 "NOTES" 6 "NETNAM" 4
"CMPNAM" 5 "BORDER" 5}
}
{USER
{VIEW
{Mode SYMB}
{Nlst OPEN}
{Vw 0 0 2}
{Lv 12 2 2 2 0 0 2 2 2 2 0 0 2 1 2 0 0 0 0}
{Gs 10 10}
}
}
{DISPLAY
[Ly "PINNUM"]
[Ls "SOLID"][Wd 0]
[Ts 15][Tj "LC"][Tr 0][Tm "N"]
}
{SYMBOL
{PIN_DEF
[Ly "PINCON"]
{P PHI2 {Pt "INPUT"}{Lq 0}{Ploc 100 240}}
{P R_W {Pt "INPUT"}{Lq 0}{Ploc 100 200}}
{P A15 {Pt "INPUT"}{Lq 0}{Ploc 100 180}}
{P A14 {Pt "INPUT"}{Lq 0}{Ploc 100 160}}
{P A13 {Pt "INPUT"}{Lq 0}{Ploc 100 140}}
{P A12 {Pt "INPUT"}{Lq 0}{Ploc 100 120}}
{P A6 {Pt "INPUT"}{Lq 0}{Ploc 100 100}}
{P A5 {Pt "INPUT"}{Lq 0}{Ploc 100 80}}
{P A4 {Pt "INPUT"}{Lq 0}{Ploc 100 60}}
{P SB0 {Pt "INPUT"}{Lq 0}{Ploc 100 40}}
{P SB1 {Pt "INPUT"}{Lq 0}{Ploc 100 20}}
{P RD' {Pt "I/O"}{Lq 0}{Ploc 310 20}}
{P WR' {Pt "I/O"}{Lq 0}{Ploc 310 40}}
{P VIA1' {Pt "I/O"}{Lq 0}{Ploc 310 60}}
{P VIA2' {Pt "I/O"}{Lq 0}{Ploc 310 80}}
{P BASERAM' {Pt "I/O"}{Lq 0}{Ploc 310 100}}
{P SWAPBA0' {Pt "I/O"}{Lq 0}{Ploc 310 120}}
{P SWAPBA1' {Pt "I/O"}{Lq 0}{Ploc 310 140}}
{P SWAPBA2' {Pt "I/O"}{Lq 0}{Ploc 310 160}}
{P SWAPBA3' {Pt "I/O"}{Lq 0}{Ploc 310 180}}
{P ROM' {Pt "I/O"}{Lq 0}{Ploc 310 200}}
}
{PKG
[Ly "REFDES"]
[Ts 25][Tj "CB"][Tr 0][Tm "N"]
{Rdl 205 270}
[Ly "PINNUM"]
[Ts 15][Tj "RC"]
{Pnl 120 250}
[Ts 15][Tj "RC"]
{Pnl 120 210}
{Pnl 120 190}
{Pnl 120 170}
{Pnl 120 150}
{Pnl 120 130}
{Pnl 120 110}
{Pnl 120 90}
{Pnl 120 70}
{Pnl 120 50}
{Pnl 120 30}
[Ts 15][Tj "LC"]
{Pnl 290 30}
{Pnl 290 50}
{Pnl 290 70}
{Pnl 290 90}
{Pnl 290 110}
{Pnl 290 130}
{Pnl 290 150}
{Pnl 290 170}
{Pnl 290 190}
{Pnl 290 210}
{Sd A 1 2 3 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 22 23}
}
{PIC
[Ly "GATE"]
[Ts 15][Tj "LC"][Tr 0][Tm "N"]
{R 130 260 280 0}
{L 130 240 100 240}
{L 130 250 140 240 130 230}
{L 130 200 100 200}
{L 130 180 100 180}
{L 130 160 100 160}
{L 130 140 100 140}
{L 130 120 100 120}
{L 130 100 100 100}
{L 130 80 100 80}
{L 130 60 100 60}
{L 130 40 100 40}
{L 130 20 100 20}
{C 285 20 5}
{L 290 20 310 20}
{C 285 40 5}
{L 290 40 310 40}
{C 285 60 5}
{L 290 60 310 60}
{C 285 80 5}
{L 290 80 310 80}
{C 285 100 5}
{L 290 100 310 100}
{C 285 120 5}
{L 290 120 310 120}
{C 285 140 5}
{L 290 140 310 140}
{C 285 160 5}
{L 290 160 310 160}
{C 285 180 5}
{L 290 180 310 180}
{C 285 200 5}
{L 290 200 310 200}
[Ly "PINNAM"]
[Tj "LC"]
{T "PHI2" 140 240}
{T "R_W" 140 200}
{T "A15" 140 180}
{T "A14" 140 160}
{T "A13" 140 140}
{T "A12" 140 120}
{T "A6" 140 100}
{T "A5" 140 80}
{T "A4" 140 60}
{T "SB0" 140 40}
{T "SB1" 140 20}
[Tj "RC"]
{T "RD'" 270 20}
{T "WR'" 270 40}
{T "VIA1'" 270 60}
{T "VIA2'" 270 80}
{T "BASERAM'" 270 100}
{T "SWAPBA0'" 270 120}
{T "SWAPBA1'" 270 140}
{T "SWAPBA2'" 270 160}
{T "SWAPBA3'" 270 180}
{T "ROM'" 270 200}
[Ly "DEVICE"]
[Tj "CT"]
{T "G22V10" 205 -10}
}
{ATR
{IN
{Org 100 20}
{Ty 255}
}
{EX
[Ly "ATTR2"]
[Ts 12][Tj "CT"][Tr 0][Tm "N"]
{At PLD E:\0_WORKSPACE\01_CUPL\6502_DECODER 205 260}
}
}
}
{DETAIL
{ANNOTATE
}
{NET_DEF
{N PHI2
}
{N R_W
}
{N A15
}
{N A14
}
{N A13
}
{N A12
}
{N A6
}
{N A5
}
{N A4
}
{N SB0
}
{N SB1
}
{N RD'
}
{N WR'
}
{N VIA1'
}
{N VIA2'
}
{N BASERAM'
}
{N SWAPBA0'
}
{N SWAPBA1'
}
{N SWAPBA2'
}
{N SWAPBA3'
}
{N ROM'
}
}
{SUBCOMP
}
}
}

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Name 6502_DECODER;
Partno Lattice22V10B;
Date 02/04/15;
Revision 01;
Designer shalewyn.com;
Company shalewyn.com;
Assembly XXXXX;
Location XXXXX;
Device g22v10;
ORDER: PHI2, R_W, !WR;
VECTORS:
ZZZ

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Name 6502_DECODER;
Partno Lattice22V10B;
Date 02/04/15;
Revision 01;
Designer shalewyn.com;
Company shalewyn.com;
Assembly XXXXX;
Location XXXXX;
Device g22v10;
/*
* Lattice GAL 22V10B pinout, DIP, top view
*
* I/CLK.[ 1 24 ].VCC
* I.[ 2 23 ].I/O/Q
* I.[ 3 22 ].I/O/Q
* I.[ 4 21 ].I/O/Q
* I.[ 5 20 ].I/O/Q
* I.[ 6 19 ].I/O/Q
* I.[ 7 18 ].I/O/Q
* I.[ 8 17 ].I/O/Q
* I.[ 9 16 ].I/O/Q
* I.[ 10 15 ].I/O/Q
* I.[ 11 14 ].I/O/Q
* GND.[ 12 13 ].I
*
*
*
* $1000-$1FFF - %0000 0000 0000 0000 - %0001 1111 1111 1111
* $2000-$7FFF - %0010 0000 0000 0000 - %0111 1111 1111 1111
* $8000-$800F - %1000 0000 0000 0000 - %1000 0000 0000 1111
* $8010-$801F - %1000 0000 0001 0000 - %1000 0000 0001 1111
* $8020-$802F - %1000 0000 0010 0000 - %1000 0000 0010 1111
* $8040-$804F - %1000 0000 0100 0000 - %1000 0000 0100 1111
* $9000-$FFFF - %1001 0000 0000 0000 - %1111 1111 1111 1111
*
*
* !Pin 17 - non-swap RAM $0000-$1FFF
* !Pin 18 - Swap bank 0 - $2000-$7FFF
* !Pin 19 - Swap bank 1 - $2000-$7FFF
* !Pin 21 - /VIA 1 - $8000-$800F
* !Pin 22 - /VIA 2 - $8010-$801F
* !Pin 23 - /ROM - $9000-$FFFF
*
*
* Inputs
*/
/* Inputs */
PIN 1 = PHI2;
PIN 2 = R_W;
PIN [3..6] = [A15..12];
PIN [7..9] = [A6..4];
PIN 10 = sb0;
PIN 11 = sb1;
/* Outputs */
PIN 14 = !RD;
PIN 15 = !WR;
PIN 16 = !VIA1;
PIN 17 = !VIA2;
PIN 18 = !BASERAM;
PIN 19 = !SWAPBANK0;
PIN 20 = !SWAPBANK1;
PIN 21 = !SWAPBANK2;
PIN 22 = !SWAPBANK3;
PIN 23 = !ROM;
/* Rules */
RD = PHI2 & R_W;
WR = PHI2 & !R_W;
BASERAM = !A15 & !A14 & !A13 & !A12;
SWAPBANK0 = !A15 & !A14 & A13 & !A12 & !sb0 & !sb1
# !A15 & !A14 & A13 & A12 & !sb0 & !sb1
# !A15 & A14 & !A13 & !A12 & !sb0 & !sb1
# !A15 & A14 & !A13 & A12 & !sb0 & !sb1
# !A15 & A14 & A13 & !A12 & !sb0 & !sb1
# !A15 & A14 & A13 & A12 & !sb0 & !sb1;
SWAPBANK1 = !A15 & !A14 & A13 & !A12 & !sb0 & sb1
# !A15 & !A14 & A13 & A12 & !sb0 & sb1
# !A15 & A14 & !A13 & !A12 & !sb0 & sb1
# !A15 & A14 & !A13 & A12 & !sb0 & sb1
# !A15 & A14 & A13 & !A12 & !sb0 & sb1
# !A15 & A14 & A13 & A12 & !sb0 & sb1;
SWAPBANK2 = !A15 & !A14 & A13 & !A12 & sb0 & !sb1
# !A15 & !A14 & A13 & A12 & sb0 & !sb1
# !A15 & A14 & !A13 & !A12 & sb0 & !sb1
# !A15 & A14 & !A13 & A12 & sb0 & !sb1
# !A15 & A14 & A13 & !A12 & sb0 & !sb1
# !A15 & A14 & A13 & A12 & sb0 & !sb1;
SWAPBANK3 = !A15 & !A14 & A13 & !A12 & !sb0 & sb1
# !A15 & !A14 & A13 & A12 & sb0 & sb1
# !A15 & A14 & !A13 & !A12 & sb0 & sb1
# !A15 & A14 & !A13 & A12 & sb0 & sb1
# !A15 & A14 & A13 & !A12 & sb0 & sb1
# !A15 & A14 & A13 & A12 & sb0 & sb1;
VIA1 = A15 & !A14 & !A13 & !A12 & !A5 & !A4;
VIA2 = A15 & !A14 & !A13 & !A12 & !A5 & A4;
ROM = A15 & !A14 & !A13 & A12
# A15 & !A14 & A13 & !A12
# A15 & !A14 & A13 & A12
# A15 & A14 & !A13 & !A12
# A15 & A14 & !A13 & A12
# A15 & A14 & A13 & !A12
# A15 & A14 & A13 & A12;