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paolo.iocco
2023-03-13 08:36:51 +00:00
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*******************************************************************************
6502_DECODER
*******************************************************************************
CUPL(WM) 5.0a Serial# 60008009
Device g22v10 Library DLIB-h-40-1
Created Tue Apr 25 11:59:30 2017
Name 6502_DECODER
Partno Lattice22V10B
Revision 01
Date 02/04/15
Designer shalewyn.com
Company shalewyn.com
Assembly XXXXX
Location XXXXX
===============================================================================
Expanded Product Terms
===============================================================================
BASERAM =>
!A12 & !A13 & !A14 & !A15
RD =>
PHI2 & R_W
ROM =>
A12 & !A14 & A15
# !A12 & A13 & A15
# !A13 & A14 & A15
# A12 & A13 & A14 & A15
SWAPBANK0 =>
A13 & !A15 & !sb0 & !sb1
# !A13 & A14 & !A15 & !sb0 & !sb1
SWAPBANK1 =>
A13 & !A15 & !sb0 & sb1
# !A13 & A14 & !A15 & !sb0 & sb1
SWAPBANK2 =>
A13 & !A15 & sb0 & !sb1
# !A13 & A14 & !A15 & sb0 & !sb1
SWAPBANK3 =>
!A12 & A13 & !A14 & !A15 & !sb0 & sb1
# A12 & A13 & !A15 & sb0 & sb1
# !A13 & A14 & !A15 & sb0 & sb1
# !A12 & A13 & A14 & !A15 & sb0 & sb1
VIA1 =>
!A4 & !A5 & !A12 & !A13 & !A14 & A15
VIA2 =>
A4 & !A5 & !A12 & !A13 & !A14 & A15
WR =>
PHI2 & !R_W
BASERAM.oe =>
1
RD.oe =>
1
ROM.oe =>
1
SWAPBANK0.oe =>
1
SWAPBANK1.oe =>
1
SWAPBANK2.oe =>
1
SWAPBANK3.oe =>
1
VIA1.oe =>
1
VIA2.oe =>
1
WR.oe =>
1
===============================================================================
Symbol Table
===============================================================================
Pin Variable Pterms Max Min
Pol Name Ext Pin Type Used Pterms Level
--- -------- --- --- ---- ------ ------ -----
A4 9 V - - -
A5 8 V - - -
A6 7 V - - -
A12 6 V - - -
A13 5 V - - -
A14 4 V - - -
A15 3 V - - -
! BASERAM 18 V 1 16 1
PHI2 1 V - - -
! RD 14 V 1 8 1
! ROM 23 V 4 8 1
R_W 2 V - - -
! SWAPBANK0 19 V 2 16 1
! SWAPBANK1 20 V 2 14 1
! SWAPBANK2 21 V 2 12 1
! SWAPBANK3 22 V 4 10 1
! VIA1 16 V 1 12 1
! VIA2 17 V 1 14 1
! WR 15 V 1 10 1
sb0 10 V - - -
sb1 11 V - - -
BASERAM oe 18 D 1 1 0
RD oe 14 D 1 1 0
ROM oe 23 D 1 1 0
SWAPBANK0 oe 19 D 1 1 0
SWAPBANK1 oe 20 D 1 1 0
SWAPBANK2 oe 21 D 1 1 0
SWAPBANK3 oe 22 D 1 1 0
VIA1 oe 16 D 1 1 0
VIA2 oe 17 D 1 1 0
WR oe 15 D 1 1 0
LEGEND D : default variable F : field G : group
I : intermediate variable N : node M : extended node
U : undefined V : variable X : extended variable
T : function

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CUPL(WM) 5.0a Serial# MW-10400000
Device g22v10 Library DLIB-h-40-1
Created Tue Sep 14 16:00:25 2021
Name 6502_DECODER
Partno Lattice22V10B
Revision 01
Date 02/04/15
Designer shalewyn.com
Company shalewyn.com
Assembly XXXXX
Location XXXXX
*QP24
*QF5892
*G0
*F0
*L00032 00000000000011111111111111111111
*L00064 11111111111111111111111111111111
*L00096 01111011111101111111111111111111
*L00128 11111111111101111111011110111111
*L00160 11111111111111111111111101110111
*L00192 10111111111111111111111111111111
*L00224 11110111011101110111111111111111
*L00256 11111111000000000000000000000000
*L00416 00000000000000000000000011111111
*L00448 11111111111111111111111111111111
*L00480 11111111111110111011011110111111
*L00512 11111111101101111111111110111111
*L00544 01110111111111111111011101111111
*L00576 11111011011110111111111111111111
*L00608 01110111111111111011011101111011
*L00640 11111111111101110111000000000000
*L00896 00000000000000000000000000001111
*L00928 11111111111111111111111111111111
*L00960 11111111111111111011111101111111
*L00992 11111111111101111011111111111011
*L01024 01111011111111111111111101111011
*L01472 00000000000000000000000011111111
*L01504 11111111111111111111111111111111
*L01536 11111111111110111111011111111111
*L01568 11111111101101111111111110110111
*L01600 10111111111111111111101101110000
*L02144 00000000000011111111111111111111
*L02176 11111111111111111111111111111111
*L02208 10111111011111111111111111111011
*L02240 10111111111110110111101111111111
*L02272 11111111101110110000000000000000
*L02880 00000000000000000000000011111111
*L02912 11111111111111111111111111111111
*L02944 11111111111110111011101110111111
*L02976 11111111111111110000000000000000
*L03648 00001111111111111111111111111111
*L03680 11111111111111111111111101111011
*L03712 10111011111110110111111111110000
*L04288 00000000000000000000000011111111
*L04320 11111111111111111111111111111111
*L04352 11111111111101111011101110111111
*L04384 10111011111111110000000000000000
*L04864 00000000000000000000111111111111
*L04896 11111111111111111111111111111111
*L04928 01111011111111111111111111111111
*L04960 11111111111100000000000000000000
*L05344 00000000000000000000000011111111
*L05376 11111111111111111111111111111111
*L05408 11110111011111111111111111111111
*L05440 11111111111111110000000000000000
*L05792 00000000000000000101010101010101
*L05824 01010100110001100001011101000111
*L05856 01000110100101100011011001010011
*L05888 0010
*CA0D3
*F852

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{COMPONENT E:\0_WORKSPACE\01_CUPL\6502_DECODER.SYM
{ENVIRONMENT
{PDIFvrev 3.00}
{Program "CUPL(WM) Version 5.0a"}
{DBtype "Schematic"}
{DBvrev 1.01}
{DBtime "Tue Apr 25 11:59:30 2017 "}
{DBunit "MIL"}
{DBgrid 10}
{Lyrstr "WIRES" 1 "BUS" 1 "GATE" 2 "IEEE" 2 "PINFUN" 3 "PINNUM" 1
"PINNAM" 6 "PINCON" 4 "REFDES" 2 "ATTR" 6 "SDOT" 1
"DEVICE" 5 "OUTLIN" 5 "ATTR2" 6 "NOTES" 6 "NETNAM" 4
"CMPNAM" 5 "BORDER" 5}
}
{USER
{VIEW
{Mode SYMB}
{Nlst OPEN}
{Vw 0 0 2}
{Lv 12 2 2 2 0 0 2 2 2 2 0 0 2 1 2 0 0 0 0}
{Gs 10 10}
}
}
{DISPLAY
[Ly "PINNUM"]
[Ls "SOLID"][Wd 0]
[Ts 15][Tj "LC"][Tr 0][Tm "N"]
}
{SYMBOL
{PIN_DEF
[Ly "PINCON"]
{P PHI2 {Pt "INPUT"}{Lq 0}{Ploc 100 240}}
{P R_W {Pt "INPUT"}{Lq 0}{Ploc 100 200}}
{P A15 {Pt "INPUT"}{Lq 0}{Ploc 100 180}}
{P A14 {Pt "INPUT"}{Lq 0}{Ploc 100 160}}
{P A13 {Pt "INPUT"}{Lq 0}{Ploc 100 140}}
{P A12 {Pt "INPUT"}{Lq 0}{Ploc 100 120}}
{P A6 {Pt "INPUT"}{Lq 0}{Ploc 100 100}}
{P A5 {Pt "INPUT"}{Lq 0}{Ploc 100 80}}
{P A4 {Pt "INPUT"}{Lq 0}{Ploc 100 60}}
{P SB0 {Pt "INPUT"}{Lq 0}{Ploc 100 40}}
{P SB1 {Pt "INPUT"}{Lq 0}{Ploc 100 20}}
{P RD' {Pt "I/O"}{Lq 0}{Ploc 310 20}}
{P WR' {Pt "I/O"}{Lq 0}{Ploc 310 40}}
{P VIA1' {Pt "I/O"}{Lq 0}{Ploc 310 60}}
{P VIA2' {Pt "I/O"}{Lq 0}{Ploc 310 80}}
{P BASERAM' {Pt "I/O"}{Lq 0}{Ploc 310 100}}
{P SWAPBA0' {Pt "I/O"}{Lq 0}{Ploc 310 120}}
{P SWAPBA1' {Pt "I/O"}{Lq 0}{Ploc 310 140}}
{P SWAPBA2' {Pt "I/O"}{Lq 0}{Ploc 310 160}}
{P SWAPBA3' {Pt "I/O"}{Lq 0}{Ploc 310 180}}
{P ROM' {Pt "I/O"}{Lq 0}{Ploc 310 200}}
}
{PKG
[Ly "REFDES"]
[Ts 25][Tj "CB"][Tr 0][Tm "N"]
{Rdl 205 270}
[Ly "PINNUM"]
[Ts 15][Tj "RC"]
{Pnl 120 250}
[Ts 15][Tj "RC"]
{Pnl 120 210}
{Pnl 120 190}
{Pnl 120 170}
{Pnl 120 150}
{Pnl 120 130}
{Pnl 120 110}
{Pnl 120 90}
{Pnl 120 70}
{Pnl 120 50}
{Pnl 120 30}
[Ts 15][Tj "LC"]
{Pnl 290 30}
{Pnl 290 50}
{Pnl 290 70}
{Pnl 290 90}
{Pnl 290 110}
{Pnl 290 130}
{Pnl 290 150}
{Pnl 290 170}
{Pnl 290 190}
{Pnl 290 210}
{Sd A 1 2 3 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 22 23}
}
{PIC
[Ly "GATE"]
[Ts 15][Tj "LC"][Tr 0][Tm "N"]
{R 130 260 280 0}
{L 130 240 100 240}
{L 130 250 140 240 130 230}
{L 130 200 100 200}
{L 130 180 100 180}
{L 130 160 100 160}
{L 130 140 100 140}
{L 130 120 100 120}
{L 130 100 100 100}
{L 130 80 100 80}
{L 130 60 100 60}
{L 130 40 100 40}
{L 130 20 100 20}
{C 285 20 5}
{L 290 20 310 20}
{C 285 40 5}
{L 290 40 310 40}
{C 285 60 5}
{L 290 60 310 60}
{C 285 80 5}
{L 290 80 310 80}
{C 285 100 5}
{L 290 100 310 100}
{C 285 120 5}
{L 290 120 310 120}
{C 285 140 5}
{L 290 140 310 140}
{C 285 160 5}
{L 290 160 310 160}
{C 285 180 5}
{L 290 180 310 180}
{C 285 200 5}
{L 290 200 310 200}
[Ly "PINNAM"]
[Tj "LC"]
{T "PHI2" 140 240}
{T "R_W" 140 200}
{T "A15" 140 180}
{T "A14" 140 160}
{T "A13" 140 140}
{T "A12" 140 120}
{T "A6" 140 100}
{T "A5" 140 80}
{T "A4" 140 60}
{T "SB0" 140 40}
{T "SB1" 140 20}
[Tj "RC"]
{T "RD'" 270 20}
{T "WR'" 270 40}
{T "VIA1'" 270 60}
{T "VIA2'" 270 80}
{T "BASERAM'" 270 100}
{T "SWAPBA0'" 270 120}
{T "SWAPBA1'" 270 140}
{T "SWAPBA2'" 270 160}
{T "SWAPBA3'" 270 180}
{T "ROM'" 270 200}
[Ly "DEVICE"]
[Tj "CT"]
{T "G22V10" 205 -10}
}
{ATR
{IN
{Org 100 20}
{Ty 255}
}
{EX
[Ly "ATTR2"]
[Ts 12][Tj "CT"][Tr 0][Tm "N"]
{At PLD E:\0_WORKSPACE\01_CUPL\6502_DECODER 205 260}
}
}
}
{DETAIL
{ANNOTATE
}
{NET_DEF
{N PHI2
}
{N R_W
}
{N A15
}
{N A14
}
{N A13
}
{N A12
}
{N A6
}
{N A5
}
{N A4
}
{N SB0
}
{N SB1
}
{N RD'
}
{N WR'
}
{N VIA1'
}
{N VIA2'
}
{N BASERAM'
}
{N SWAPBA0'
}
{N SWAPBA1'
}
{N SWAPBA2'
}
{N SWAPBA3'
}
{N ROM'
}
}
{SUBCOMP
}
}
}

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Name 6502_DECODER;
Partno Lattice22V10B;
Date 02/04/15;
Revision 01;
Designer shalewyn.com;
Company shalewyn.com;
Assembly XXXXX;
Location XXXXX;
Device g22v10;
ORDER: PHI2, R_W, !WR;
VECTORS:
ZZZ

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Name 6502_DECODER;
Partno Lattice22V10B;
Date 02/04/15;
Revision 01;
Designer shalewyn.com;
Company shalewyn.com;
Assembly XXXXX;
Location XXXXX;
Device g22v10;
/*
* Lattice GAL 22V10B pinout, DIP, top view
*
* I/CLK.[ 1 24 ].VCC
* I.[ 2 23 ].I/O/Q
* I.[ 3 22 ].I/O/Q
* I.[ 4 21 ].I/O/Q
* I.[ 5 20 ].I/O/Q
* I.[ 6 19 ].I/O/Q
* I.[ 7 18 ].I/O/Q
* I.[ 8 17 ].I/O/Q
* I.[ 9 16 ].I/O/Q
* I.[ 10 15 ].I/O/Q
* I.[ 11 14 ].I/O/Q
* GND.[ 12 13 ].I
*
*
*
* $1000-$1FFF - %0000 0000 0000 0000 - %0001 1111 1111 1111
* $2000-$7FFF - %0010 0000 0000 0000 - %0111 1111 1111 1111
* $8000-$800F - %1000 0000 0000 0000 - %1000 0000 0000 1111
* $8010-$801F - %1000 0000 0001 0000 - %1000 0000 0001 1111
* $8020-$802F - %1000 0000 0010 0000 - %1000 0000 0010 1111
* $8040-$804F - %1000 0000 0100 0000 - %1000 0000 0100 1111
* $9000-$FFFF - %1001 0000 0000 0000 - %1111 1111 1111 1111
*
*
* !Pin 17 - non-swap RAM $0000-$1FFF
* !Pin 18 - Swap bank 0 - $2000-$7FFF
* !Pin 19 - Swap bank 1 - $2000-$7FFF
* !Pin 21 - /VIA 1 - $8000-$800F
* !Pin 22 - /VIA 2 - $8010-$801F
* !Pin 23 - /ROM - $9000-$FFFF
*
*
* Inputs
*/
/* Inputs */
PIN 1 = PHI2;
PIN 2 = R_W;
PIN [3..6] = [A15..12];
PIN [7..9] = [A6..4];
PIN 10 = sb0;
PIN 11 = sb1;
/* Outputs */
PIN 14 = !RD;
PIN 15 = !WR;
PIN 16 = !VIA1;
PIN 17 = !VIA2;
PIN 18 = !BASERAM;
PIN 19 = !SWAPBANK0;
PIN 20 = !SWAPBANK1;
PIN 21 = !SWAPBANK2;
PIN 22 = !SWAPBANK3;
PIN 23 = !ROM;
/* Rules */
RD = PHI2 & R_W;
WR = PHI2 & !R_W;
BASERAM = !A15 & !A14 & !A13 & !A12;
SWAPBANK0 = !A15 & !A14 & A13 & !A12 & !sb0 & !sb1
# !A15 & !A14 & A13 & A12 & !sb0 & !sb1
# !A15 & A14 & !A13 & !A12 & !sb0 & !sb1
# !A15 & A14 & !A13 & A12 & !sb0 & !sb1
# !A15 & A14 & A13 & !A12 & !sb0 & !sb1
# !A15 & A14 & A13 & A12 & !sb0 & !sb1;
SWAPBANK1 = !A15 & !A14 & A13 & !A12 & !sb0 & sb1
# !A15 & !A14 & A13 & A12 & !sb0 & sb1
# !A15 & A14 & !A13 & !A12 & !sb0 & sb1
# !A15 & A14 & !A13 & A12 & !sb0 & sb1
# !A15 & A14 & A13 & !A12 & !sb0 & sb1
# !A15 & A14 & A13 & A12 & !sb0 & sb1;
SWAPBANK2 = !A15 & !A14 & A13 & !A12 & sb0 & !sb1
# !A15 & !A14 & A13 & A12 & sb0 & !sb1
# !A15 & A14 & !A13 & !A12 & sb0 & !sb1
# !A15 & A14 & !A13 & A12 & sb0 & !sb1
# !A15 & A14 & A13 & !A12 & sb0 & !sb1
# !A15 & A14 & A13 & A12 & sb0 & !sb1;
SWAPBANK3 = !A15 & !A14 & A13 & !A12 & !sb0 & sb1
# !A15 & !A14 & A13 & A12 & sb0 & sb1
# !A15 & A14 & !A13 & !A12 & sb0 & sb1
# !A15 & A14 & !A13 & A12 & sb0 & sb1
# !A15 & A14 & A13 & !A12 & sb0 & sb1
# !A15 & A14 & A13 & A12 & sb0 & sb1;
VIA1 = A15 & !A14 & !A13 & !A12 & !A5 & !A4;
VIA2 = A15 & !A14 & !A13 & !A12 & !A5 & A4;
ROM = A15 & !A14 & !A13 & A12
# A15 & !A14 & A13 & !A12
# A15 & !A14 & A13 & A12
# A15 & A14 & !A13 & !A12
# A15 & A14 & !A13 & A12
# A15 & A14 & A13 & !A12
# A15 & A14 & A13 & A12;

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Name Adder;
Partno CA0016;
Date 08/10/1999;
Rev 01;
Designer Woolhiser;
Company Assisted Technology;
Assembly None;
Location None;
Device G16V8;
/****************************************************************/
/* */
/* Four bit adder using the CUPL function statement. */
/* */
/* 4-bit asynchronous adder implemented as a ripple-carry */
/* through four adder-slice circuits. Each adder-slice */
/* takes a pair of 1-bit numbers (Xi, Yi) and the carry from */
/* a previous slice (Cin) and produces their 1-bit sum (Zi) */
/* and carry (Cout). Each adder-slice circuit is defined */
/* using the CUPL function adder_slice(), which returns */
/* the product directly and the carry as Cout. */
/****************************************************************/
/** Inputs **/
Pin [1..4] = [X1..4]; /* First 4-bit number */
Pin [5..8] = [Y1..4]; /* Second 4-bit number */
/** Outputs **/
Pin [12..15] = [Z1..4]; /* 4-bit sum */
Pin [16..18] = [C1..3]; /* Intermediate carry vaules */
Pin 19 = Carry; /* Carry for 4-bit sum */
/* Adder-slice circuit - add 2, 1-bit, numbers with carry */
function adder_slice(X, Y, Cin, Cout) {
Cout = Cin & X /* Compute carry */
# Cin & Y
# X & Y;
adder_slice = Cin $ (X $ Y); /* Compute sum */
}
/* Perform 4, 1-bit, additions and keep the final carry */
Z1 = adder_slice(X1, Y1, 'h'0, C1); /* Initial carry = 'h'0 */
Z2 = adder_slice(X2, Y2, C1, C2);
Z3 = adder_slice(X3, Y3, C2, C3);
Z4 = adder_slice(X4, Y4, C3, Carry); /* Get final carry value */

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*******************************************************************************
Adder
*******************************************************************************
CUPL(WM) 5.0a Serial# 60008009
Device g16v8ma Library DLIB-h-40-8
Created Tue Apr 25 12:02:15 2017
Name Adder
Partno CA0016
Revision 01
Date 08/10/1999
Designer Woolhiser
Company Assisted Technology
Assembly None
Location None
===============================================================================
Expanded Product Terms
===============================================================================
C1 =>
X1 & Y1
C2 =>
C1 & X2
# C1 & Y2
# X2 & Y2
C3 =>
C2 & X3
# C2 & Y3
# X3 & Y3
Carry =>
C3 & X4
# C3 & Y4
# X4 & Y4
Z1 =>
X1 & !Y1
# !X1 & Y1
Z2 =>
C1 & X2 & Y2
# C1 & !X2 & !Y2
# !C1 & !X2 & Y2
# !C1 & X2 & !Y2
Z3 =>
C2 & X3 & Y3
# C2 & !X3 & !Y3
# !C2 & !X3 & Y3
# !C2 & X3 & !Y3
Z4 =>
C3 & X4 & Y4
# C3 & !X4 & !Y4
# !C3 & !X4 & Y4
# !C3 & X4 & !Y4
C1.oe =>
1
C2.oe =>
1
C3.oe =>
1
Carry.oe =>
1
Z1.oe =>
1
Z2.oe =>
1
Z3.oe =>
1
Z4.oe =>
1
===============================================================================
Symbol Table
===============================================================================
Pin Variable Pterms Max Min
Pol Name Ext Pin Type Used Pterms Level
--- -------- --- --- ---- ------ ------ -----
C1 16 V 1 7 1
C2 17 V 3 7 1
C3 18 V 3 7 1
Carry 19 V 3 7 1
X1 1 V - - -
X2 2 V - - -
X3 3 V - - -
X4 4 V - - -
Y1 5 V - - -
Y2 6 V - - -
Y3 7 V - - -
Y4 8 V - - -
Z1 12 V 2 7 1
Z2 13 V 4 7 1
Z3 14 V 4 7 1
Z4 15 V 4 7 1
adder_slice 0 T - - -
C1 oe 16 D 1 1 0
C2 oe 17 D 1 1 0
C3 oe 18 D 1 1 0
Carry oe 19 D 1 1 0
Z1 oe 12 D 1 1 0
Z2 oe 13 D 1 1 0
Z3 oe 14 D 1 1 0
Z4 oe 15 D 1 1 0
LEGEND D : default variable F : field G : group
I : intermediate variable N : node M : extended node
U : undefined V : variable X : extended variable
T : function

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{COMPONENT E:\0_WORKSPACE\01_CUPL\ADDER.SYM
{ENVIRONMENT
{PDIFvrev 3.00}
{Program "CUPL(WM) Version 5.0a"}
{DBtype "Schematic"}
{DBvrev 1.01}
{DBtime "Tue Apr 25 12:02:15 2017 "}
{DBunit "MIL"}
{DBgrid 10}
{Lyrstr "WIRES" 1 "BUS" 1 "GATE" 2 "IEEE" 2 "PINFUN" 3 "PINNUM" 1
"PINNAM" 6 "PINCON" 4 "REFDES" 2 "ATTR" 6 "SDOT" 1
"DEVICE" 5 "OUTLIN" 5 "ATTR2" 6 "NOTES" 6 "NETNAM" 4
"CMPNAM" 5 "BORDER" 5}
}
{USER
{VIEW
{Mode SYMB}
{Nlst OPEN}
{Vw 0 0 2}
{Lv 12 2 2 2 0 0 2 2 2 2 0 0 2 1 2 0 0 0 0}
{Gs 10 10}
}
}
{DISPLAY
[Ly "PINNUM"]
[Ls "SOLID"][Wd 0]
[Ts 15][Tj "LC"][Tr 0][Tm "N"]
}
{SYMBOL
{PIN_DEF
[Ly "PINCON"]
{P X1 {Pt "INPUT"}{Lq 0}{Ploc 100 160}}
{P X2 {Pt "INPUT"}{Lq 0}{Ploc 100 140}}
{P X3 {Pt "INPUT"}{Lq 0}{Ploc 100 120}}
{P X4 {Pt "INPUT"}{Lq 0}{Ploc 100 100}}
{P Y1 {Pt "INPUT"}{Lq 0}{Ploc 100 80}}
{P Y2 {Pt "INPUT"}{Lq 0}{Ploc 100 60}}
{P Y3 {Pt "INPUT"}{Lq 0}{Ploc 100 40}}
{P Y4 {Pt "INPUT"}{Lq 0}{Ploc 100 20}}
{P Z1 {Pt "I/O"}{Lq 0}{Ploc 280 20}}
{P Z2 {Pt "I/O"}{Lq 0}{Ploc 280 40}}
{P Z3 {Pt "I/O"}{Lq 0}{Ploc 280 60}}
{P Z4 {Pt "I/O"}{Lq 0}{Ploc 280 80}}
{P C1 {Pt "I/O"}{Lq 0}{Ploc 280 100}}
{P C2 {Pt "I/O"}{Lq 0}{Ploc 280 120}}
{P C3 {Pt "I/O"}{Lq 0}{Ploc 280 140}}
{P CARRY {Pt "I/O"}{Lq 0}{Ploc 280 160}}
}
{PKG
[Ly "REFDES"]
[Ts 25][Tj "CB"][Tr 0][Tm "N"]
{Rdl 190 190}
[Ly "PINNUM"]
[Ts 15][Tj "RC"]
{Pnl 120 170}
{Pnl 120 150}
{Pnl 120 130}
{Pnl 120 110}
{Pnl 120 90}
{Pnl 120 70}
{Pnl 120 50}
{Pnl 120 30}
[Ts 15][Tj "LC"]
{Pnl 260 30}
{Pnl 260 50}
{Pnl 260 70}
{Pnl 260 90}
{Pnl 260 110}
{Pnl 260 130}
{Pnl 260 150}
{Pnl 260 170}
{Sd A 1 2 3 4 5 6 7 8 12 13 14 15 16 17 18 19}
}
{PIC
[Ly "GATE"]
[Ts 15][Tj "LC"][Tr 0][Tm "N"]
{R 130 180 250 0}
{L 130 160 100 160}
{L 130 140 100 140}
{L 130 120 100 120}
{L 130 100 100 100}
{L 130 80 100 80}
{L 130 60 100 60}
{L 130 40 100 40}
{L 130 20 100 20}
{L 250 20 280 20}
{L 250 40 280 40}
{L 250 60 280 60}
{L 250 80 280 80}
{L 250 100 280 100}
{L 250 120 280 120}
{L 250 140 280 140}
{L 250 160 280 160}
[Ly "PINNAM"]
[Tj "LC"]
{T "X1" 140 160}
{T "X2" 140 140}
{T "X3" 140 120}
{T "X4" 140 100}
{T "Y1" 140 80}
{T "Y2" 140 60}
{T "Y3" 140 40}
{T "Y4" 140 20}
[Tj "RC"]
{T "Z1" 240 20}
{T "Z2" 240 40}
{T "Z3" 240 60}
{T "Z4" 240 80}
{T "C1" 240 100}
{T "C2" 240 120}
{T "C3" 240 140}
{T "CARRY" 240 160}
[Ly "DEVICE"]
[Tj "CT"]
{T "G16V8MA" 190 -10}
}
{ATR
{IN
{Org 100 20}
{Ty 255}
}
{EX
[Ly "ATTR2"]
[Ts 12][Tj "CT"][Tr 0][Tm "N"]
{At PLD E:\0_WORKSPACE\01_CUPL\ADDER 190 180}
}
}
}
{DETAIL
{ANNOTATE
}
{NET_DEF
{N X1
}
{N X2
}
{N X3
}
{N X4
}
{N Y1
}
{N Y2
}
{N Y3
}
{N Y4
}
{N Z1
}
{N Z2
}
{N Z3
}
{N Z4
}
{N C1
}
{N C2
}
{N C3
}
{N CARRY
}
}
{SUBCOMP
}
}
}

55
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CUPL(WM) 5.0a Serial# 60008009
Device g16v8ma Library DLIB-h-40-8
Created Tue Apr 25 12:02:15 2017
Name Adder
Partno CA0016
Revision 01
Date 08/10/1999
Designer Woolhiser
Company Assisted Technology
Assembly None
Location None
*QP20
*QF2194
*G0
*F0
*L00000 11111111111111111111111111111111
*L00032 11111101011111111111111111111111
*L00064 11111101111111111111111101111111
*L00096 11111111011111111111111101111111
*L00256 11111111111111111111111111111111
*L00288 11110111110111111111111111111111
*L00320 11111111110111111111011111111111
*L00352 11110111111111111111011111111111
*L00512 11111111111111111111111111111111
*L00544 01111111111111011111111111111111
*L00576 11111111111111010111111111111111
*L00608 01111111111111110111111111111111
*L00768 11111111111111111111111111111111
*L00800 11011111111101111111111111111111
*L01024 11111111111111111111111111111111
*L01056 11111101011111111111111101111111
*L01088 11111101101111111111111110111111
*L01120 11111110101111111111111101111111
*L01152 11111110011111111111111110111111
*L01280 11111111111111111111111111111111
*L01312 11110111110111111111011111111111
*L01344 11111011110111111111101111111111
*L01376 11111011111011111111011111111111
*L01408 11110111111011111111101111111111
*L01536 11111111111111111111111111111111
*L01568 01111111111111010111111111111111
*L01600 10111111111111011011111111111111
*L01632 10111111111111100111111111111111
*L01664 01111111111111101011111111111111
*L01792 11111111111111111111111111111111
*L01824 11011111111110111111111111111111
*L01856 11101111111101111111111111111111
*L02048 11111111010000110100000100110000
*L02080 00110000001100010011011000000000
*L02112 00000000111111111111111111111111
*L02144 11111111111111111111111111111111
*L02176 111111111111111111
*C863D
*74CE

62
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*******************************************************************************
Amiga_Dec
*******************************************************************************
CUPL(WM) 5.0a Serial# 60008009
Device virtual Library DLIB-h-40-1
Created Thu Apr 27 10:37:26 2017
Name Amiga_Dec
Partno g16v8
Revision 00
Date 27/04/17
Designer Paolo Iocco
Company GC73
Assembly 00
Location Munich
===============================================================================
Expanded Product Terms
===============================================================================
MOT_e =>
!DIR & MOTx
# DIR & MOT0
MOT_i =>
!DIR & MOT0
# DIR & MOTx
SEL_e =>
!DIR & SEL1
# DIR & SEL0
SEL_i =>
!DIR & SEL0
# DIR & SEL1
===============================================================================
Symbol Table
===============================================================================
Pin Variable Pterms Max Min
Pol Name Ext Pin Type Used Pterms Level
--- -------- --- --- ---- ------ ------ -----
DIR 6 V - - -
MOT0 3 V - - -
MOT_e 16 V 2 0 1
MOT_i 18 V 2 0 1
MOTx 5 V - - -
SEL0 2 V - - -
SEL1 4 V - - -
SEL_e 17 V 2 0 1
SEL_i 19 V 2 0 1
LEGEND D : default variable F : field G : group
I : intermediate variable N : node M : extended node
U : undefined V : variable X : extended variable
T : function

139
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{COMPONENT Z:\HOME\PAOLO\WORKSPACE\01_CUPL\AMIGA_FLOPPY\AMIGA_DEC.SYM
{ENVIRONMENT
{PDIFvrev 3.00}
{Program "CUPL(WM) Version 5.0a"}
{DBtype "Schematic"}
{DBvrev 1.01}
{DBtime "Tue May 09 21:37:35 2017 "}
{DBunit "MIL"}
{DBgrid 10}
{Lyrstr "WIRES" 1 "BUS" 1 "GATE" 2 "IEEE" 2 "PINFUN" 3 "PINNUM" 1
"PINNAM" 6 "PINCON" 4 "REFDES" 2 "ATTR" 6 "SDOT" 1
"DEVICE" 5 "OUTLIN" 5 "ATTR2" 6 "NOTES" 6 "NETNAM" 4
"CMPNAM" 5 "BORDER" 5}
}
{USER
{VIEW
{Mode SYMB}
{Nlst OPEN}
{Vw 0 0 2}
{Lv 12 2 2 2 0 0 2 2 2 2 0 0 2 1 2 0 0 0 0}
{Gs 10 10}
}
}
{DISPLAY
[Ly "PINNUM"]
[Ls "SOLID"][Wd 0]
[Ts 15][Tj "LC"][Tr 0][Tm "N"]
}
{SYMBOL
{PIN_DEF
[Ly "PINCON"]
{P SEL0 {Pt "INPUT"}{Lq 0}{Ploc 100 160}}
{P MOT0 {Pt "INPUT"}{Lq 0}{Ploc 100 140}}
{P SEL1 {Pt "INPUT"}{Lq 0}{Ploc 100 120}}
{P MOTX {Pt "INPUT"}{Lq 0}{Ploc 100 100}}
{P DIR {Pt "INPUT"}{Lq 0}{Ploc 100 80}}
{P SEL_E {Pt "INPUT"}{Lq 0}{Ploc 100 60}}
{P MOT_I {Pt "INPUT"}{Lq 0}{Ploc 100 40}}
{P SEL_I {Pt "INPUT"}{Lq 0}{Ploc 100 20}}
{P MOT_E {Pt "I/O"}{Lq 0}{Ploc 300 20}}
}
{PKG
[Ly "REFDES"]
[Ts 25][Tj "CB"][Tr 0][Tm "N"]
{Rdl 200 190}
[Ly "PINNUM"]
[Ts 15][Tj "RC"]
{Pnl 120 170}
{Pnl 120 150}
{Pnl 120 130}
{Pnl 120 110}
{Pnl 120 90}
{Pnl 120 70}
{Pnl 120 50}
{Pnl 120 30}
[Ts 15][Tj "LC"]
{Pnl 280 30}
{Sd A 2 3 4 5 6 17 18 19 16}
}
{PIC
[Ly "GATE"]
[Ts 15][Tj "LC"][Tr 0][Tm "N"]
{R 130 180 270 0}
{L 130 160 100 160}
{L 130 140 100 140}
{L 130 120 100 120}
{L 130 100 100 100}
{L 130 80 100 80}
{L 130 60 100 60}
{L 130 40 100 40}
{L 130 20 100 20}
{L 270 20 300 20}
[Ly "PINNAM"]
[Tj "LC"]
{T "SEL0" 140 160}
{T "MOT0" 140 140}
{T "SEL1" 140 120}
{T "MOTX" 140 100}
{T "DIR" 140 80}
{T "SEL_E" 140 60}
{T "MOT_I" 140 40}
{T "SEL_I" 140 20}
[Tj "RC"]
{T "MOT_E" 260 20}
[Ly "DEVICE"]
[Tj "CT"]
{T "G16V8S" 200 -10}
}
{ATR
{IN
{Org 100 20}
{Ty 255}
}
{EX
[Ly "ATTR2"]
[Ts 12][Tj "CT"][Tr 0][Tm "N"]
{At PLD Z:\HOME\PAOLO\WORKSPACE\01_CUPL\AMIGA_FLOPPY\AMIGA_DEC 200 180}
}
}
}
{DETAIL
{ANNOTATE
}
{NET_DEF
{N SEL0
}
{N MOT0
}
{N SEL1
}
{N MOTX
}
{N DIR
}
{N SEL_E
}
{N MOT_I
}
{N SEL_I
}
{N MOT_E
}
}
{SUBCOMP
}
}
}

47
trunk/workspace/01_CUPL/Amiga_Floppy/AMIGA_DEC.si Normal file
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Name Amiga_Dec;
PartNo g16v8;
Date 27/04/17;
Revision 00;
Designer Paolo Iocco;
Company GC73;
Assembly 00;
Location Munich;
Device G16V8;
ORDER: DIR, SEL0, MOT0, SEL1, MOTx, SEL_i, MOT_i, SEL_e, MOT_e;
VECTORS:
00000****
00001****
00010****
00011****
00100****
00101****
00110****
00111****
01000****
01001****
01010****
01011****
01100****
01101****
01110****
01111****
10000****
10001****
10010****
10011****
10100****
10101****
10110****
10111****
11000****
11001****
11010****
11011****
11100****
11101****
11110****
11111****

36
trunk/workspace/01_CUPL/Amiga_Floppy/Amiga_Dec.pld Normal file
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Name Amiga_Dec;
Partno g16v8;
Date 27/04/17;
Revision 00;
Designer Paolo Iocco;
Company GC73;
Assembly 00;
Location Munich;
Device G16V8;
/* ********************************* */
/* Amiga Floppy decoder and selector */
/* ********************************* */
/** Inputs **/
pin 2 = SEL0;
pin 3 = MOT0;
pin 4 = SEL1;
pin 5 = MOTx;
pin 6 = DIR;
/** Outputs **/
pin 19 = SEL_i;
pin 18 = MOT_i;
pin 17 = SEL_e;
pin 16 = MOT_e;
/** Logic Equations **/
SEL_i = (SEL0 & (DIR:0)) # (SEL1 & (DIR:1)) ;
MOT_i = (MOT0 & (DIR:0)) # (MOTx & (DIR:1)) ;
SEL_e = (SEL1 & (DIR:0)) # (SEL0 & (DIR:1)) ;
MOT_e = (MOTx & (DIR:0)) # (MOT0 & (DIR:1)) ;

13
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[{000214A0-0000-0000-C000-000000000046}]
Prop4=31,CUPL Tutorial
Prop3=19,11
[{A7AF692E-098D-4C08-A225-D433CA835ED0}]
Prop5=3,0
Prop9=19,0
Prop2=65,2C00000000000000010000000083FFFF0083FFFFFFFFFFFFFFFFFFFF00000000210000002604000084030000F9
Prop6=3,1
[InternetShortcut]
URL=https://class.ee.washington.edu/475/peckol/doc/cupl.html
IDList=
[{9F4C2855-9F79-4B39-A8D0-E1D42DE1D5F3}]
Prop5=8,Microsoft.Website.F5D2630F.DF043714

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trunk/workspace/01_CUPL/Z80_DEcoder_Paolo/Z80_DEC.abs Normal file
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*******************************************************************************
Z80_DEC
*******************************************************************************
CUPL(WM) 5.0a Serial# MW-10400000
Device g16v8ms Library DLIB-h-40-11
Created Mon Oct 18 12:02:34 2021
Name Z80_DEC
Partno g16v8
Revision 00
Date 14/09/21
Designer Paolo Iocco
Company GC73
Assembly 00
Location Munich
===============================================================================
Fuse Plot
===============================================================================
Syn 02192 x Ac0 02193 -
Pin #19 02048 Pol - 02120 Ac1 x
00000 ---x----------------------------
00032 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00064 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00096 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00128 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00160 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00192 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00224 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Pin #18 02049 Pol x 02121 Ac1 -
00256 --------------------------------
00288 -x------------------------------
00320 ----x---------------------------
00352 --------x-----------------------
00384 -------------x------------------
00416 ----------------x---------------
00448 --------------------x-----------
00480 ----------------------------x---
Pin #17 02050 Pol x 02122 Ac1 -
00512 --------------------------------
00544 -x------------------------------
00576 ----x---------------------------
00608 --------x-----------------------
00640 -------------x------------------
00672 ----------------x---------------
00704 --------------------x-----------
00736 ------------------------x-------
Pin #16 02051 Pol x 02123 Ac1 -
00768 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00800 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00832 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00864 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00896 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00928 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00960 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
00992 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Pin #15 02052 Pol - 02124 Ac1 -
01024 --------------------------------
01056 -----x---x---x---x--x--------xx-
01088 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01120 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01152 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01184 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01216 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01248 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Pin #14 02053 Pol - 02125 Ac1 -
01280 --------------------------------
01312 ----------------------------x---
01344 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01376 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01408 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01440 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01472 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01504 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Pin #13 02054 Pol - 02126 Ac1 -
01536 --------------------------------
01568 ------------------------x-------
01600 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01632 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01664 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01696 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01728 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01760 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Pin #12 02055 Pol x 02127 Ac1 -
01792 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01824 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01856 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01888 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01920 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01952 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
01984 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
02016 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
LEGEND X : fuse not blown
- : fuse blown
===============================================================================
Chip Diagram
===============================================================================
______________
| Z80_DEC |
CLK_IN x---|1 20|---x Vcc
!MREQ x---|2 19|---x CLK_OUT
!IORQ x---|3 18|---x PSG_BDIR
A7 x---|4 17|---x PSG_BC1
A6 x---|5 16|---x
A5 x---|6 15|---x LCD_EN
A4 x---|7 14|---x LCD_RW
A0 x---|8 13|---x LCD_RS
!WR x---|9 12|---x !M1
GND x---|10 11|---x
|______________|

345
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CUPL(WM) 5.0a Serial# 60008009
Device g16v8ms Library DLIB-h-40-11
Created Thu Nov 18 22:29:30 2021
Name Z80_DEC
Partno g16v8
Revision 00
Date 14/09/21
Designer Paolo Iocco
Company GC73
Assembly 00
Location Munich
*QP20
*QF2194
*QV297
*G0
*F0
*L00000 11101111111111111111111111111111
*L00256 11111111111111111111111111111111
*L00288 10111111111111111111111111111111
*L00320 11110111111111111111111111111111
*L00352 11111111011111111111111111111111
*L00384 11111111111110111111111111111111
*L00416 11111111111111110111111111111111
*L00448 11111111111111111111011111111111
*L00480 11111111111111111111111111110111
*L00512 11111111111111111111111111111111
*L00544 10111111111111111111111111111111
*L00576 11110111111111111111111111111111
*L00608 11111111011111111111111111111111
*L00640 11111111111110111111111111111111
*L00672 11111111111111110111111111111111
*L00704 11111111111111111111011111111111
*L00736 11111111111111111111111101111111
*L01024 11111111111111111111111111111111
*L01056 01111011101110111011011111111011
*L01280 11111111111111111111111111111111
*L01312 11111111111111111111111111110111
*L01536 11111111111111111111111111111111
*L01568 11111111111111111111111101111111
*L02048 10001110011001110011000100110110
*L02080 01110110001110000000000000000000
*L02112 00000000011111111111111111111111
*L02144 11111111111111111111111111111111
*L02176 111111111111111101
*C664E
*P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
*V0001 XX0000000NX0XXLXLLXN
*V0002 XX0000001NX0XXLXLLXN
*V0003 XX0000010NX0XXLXLLXN
*V0004 XX0000011NX0XXLXLLXN
*V0005 XX0000100NX0XXXXLLXN
*V0006 XX0000101NX0XXLXLLXN
*V0007 XX0000110NX0XXXXLLXN
*V0008 XX0000111NX0XXLXLLXN
*V0009 XX0001000NX0XXLXLLXN
*V0010 XX0001001NX0XXLXLLXN
*V0011 XX0001010NX0XXLXLLXN
*V0012 XX0001011NX0XXLXLLXN
*V0013 XX0001100NX0XXLXLLXN
*V0014 XX0001101NX0XXLXLLXN
*V0015 XX0001110NX0XXLXLLXN
*V0016 XX0001111NX0XXLXLLXN
*V0017 XX0010000NX0XXLXXXXN
*V0018 XX0010001NX0XXLXXLXN
*V0019 XX0010010NX0XXLXLXXN
*V0020 XX0010011NX0XXLXLLXN
*V0021 XX0010100NX0XXLXLLXN
*V0022 XX0010101NX0XXLXLLXN
*V0023 XX0010110NX0XXLXLLXN
*V0024 XX0010111NX0XXLXLLXN
*V0025 XX0011000NX0XXLXLLXN
*V0026 XX0011001NX0XXLXLLXN
*V0027 XX0011010NX0XXLXLLXN
*V0028 XX0011011NX0XXLXLLXN
*V0029 XX0011100NX0XXLXLLXN
*V0030 XX0011101NX0XXLXLLXN
*V0031 XX0011110NX0XXLXLLXN
*V0032 XX0011111NX0XXLXLLXN
*V0033 XX0100000NX0XXLXLLXN
*V0034 XX0100001NX0XXLXLLXN
*V0035 XX0100010NX0XXLXLLXN
*V0036 XX0100011NX0XXLXLLXN
*V0037 XX0100100NX0XXLXLLXN
*V0038 XX0100101NX0XXLXLLXN
*V0039 XX0100110NX0XXLXLLXN
*V0040 XX0100111NX0XXLXLLXN
*V0041 XX0101000NX0XXLXLLXN
*V0042 XX0101001NX0XXLXLLXN
*V0043 XX0101010NX0XXLXLLXN
*V0044 XX0101011NX0XXLXLLXN
*V0045 XX0101100NX0XXLXLLXN
*V0046 XX0101101NX0XXLXLLXN
*V0047 XX0101110NX0XXLXLLXN
*V0048 XX0101111NX0XXLXLLXN
*V0049 XX0110000NX0XXLXLLXN
*V0050 XX0110001NX0XXLXLLXN
*V0051 XX0110010NX0XXLXLLXN
*V0052 XX0110011NX0XXLXLLXN
*V0053 XX0110100NX0XXLXLLXN
*V0054 XX0110101NX0XXLXLLXN
*V0055 XX0110110NX0XXLXLLXN
*V0056 XX0110111NX0XXLXLLXN
*V0057 XX0111000NX0XXLXLLXN
*V0058 XX0111001NX0XXLXLLXN
*V0059 XX0111010NX0XXLXLLXN
*V0060 XX0111011NX0XXLXLLXN
*V0061 XX0111100NX0XXLXLLXN
*V0062 XX0111101NX0XXLXLLXN
*V0063 XX0111110NX0XXLXLLXN
*V0064 XX0111111NX0XXLXLLXN
*V0065 XX1000000NX0XXLXLLXN
*V0066 XX1000001NX0XXLXLLXN
*V0067 XX1000010NX0XXLXLLXN
*V0068 XX1000011NX0XXLXLLXN
*V0069 XX1000100NX0XXLXLLXN
*V0070 XX1000101NX0XXLXLLXN
*V0071 XX1000110NX0XXLXLLXN
*V0072 XX1000111NX0XXLXLLXN
*V0073 XX1001000NX0XXLXLLXN
*V0074 XX1001001NX0XXLXLLXN
*V0075 XX1001010NX0XXLXLLXN
*V0076 XX1001011NX0XXLXLLXN
*V0077 XX1001100NX0XXLXLLXN
*V0078 XX1001101NX0XXLXLLXN
*V0079 XX1001110NX0XXLXLLXN
*V0080 XX1001111NX0XXLXLLXN
*V0081 XX1010000NX0XXLXLLXN
*V0082 XX1010001NX0XXLXLLXN
*V0083 XX1010010NX0XXLXLLXN
*V0084 XX1010011NX0XXLXLLXN
*V0085 XX1010100NX0XXLXLLXN
*V0086 XX1010101NX0XXLXLLXN
*V0087 XX1010110NX0XXLXLLXN
*V0088 XX1010111NX0XXLXLLXN
*V0089 XX1011000NX0XXLXLLXN
*V0090 XX1011001NX0XXLXLLXN
*V0091 XX1011010NX0XXLXLLXN
*V0092 XX1011011NX0XXLXLLXN
*V0093 XX1011100NX0XXLXLLXN
*V0094 XX1011101NX0XXLXLLXN
*V0095 XX1011110NX0XXLXLLXN
*V0096 XX1011111NX0XXLXLLXN
*V0097 XX1100000NX0XXLXLLXN
*V0098 XX1100001NX0XXLXLLXN
*V0099 XX1100010NX0XXLXLLXN
*V0100 XX1100011NX0XXLXLLXN
*V0101 XX1100100NX0XXLXLLXN
*V0102 XX1100101NX0XXLXLLXN
*V0103 XX1100110NX0XXLXLLXN
*V0104 XX1100111NX0XXLXLLXN
*V0105 XX1101000NX0XXLXLLXN
*V0106 XX1101001NX0XXLXLLXN
*V0107 XX1101010NX0XXLXLLXN
*V0108 XX1101011NX0XXLXLLXN
*V0109 XX1101100NX0XXLXLLXN
*V0110 XX1101101NX0XXLXLLXN
*V0111 XX1101110NX0XXLXLLXN
*V0112 XX1101111NX0XXLXLLXN
*V0113 XX1110000NX0XXLXLLXN
*V0114 XX1110001NX0XXLXLLXN
*V0115 XX1110010NX0XXLXLLXN
*V0116 XX1110011NX0XXLXLLXN
*V0117 XX1110100NX0XXLXLLXN
*V0118 XX1110101NX0XXLXLLXN
*V0119 XX1110110NX0XXLXLLXN
*V0120 XX1110111NX0XXLXLLXN
*V0121 XX1111000NX0XXLXLLXN
*V0122 XX1111001NX0XXLXLLXN
*V0123 XX1111010NX0XXLXLLXN
*V0124 XX1111011NX0XXLXLLXN
*V0125 XX1111100NX0XXLXLLXN
*V0126 XX1111101NX0XXLXLLXN
*V0127 XX1111110NX0XXLXLLXN
*V0128 XX1111111NX0XXLXLLXN
*V0129 XX0000000NX1XXLXLLXN
*V0130 XX0000001NX1XXLXLLXN
*V0131 XX0000010NX1XXLXLLXN
*V0132 XX0000011NX1XXLXLLXN
*V0133 XX0000100NX1XXXXLLXN
*V0134 XX0000101NX1XXLXLLXN
*V0135 XX0000110NX1XXXXLLXN
*V0136 XX0000111NX1XXLXLLXN
*V0137 XX0001000NX1XXLXLLXN
*V0138 XX0001001NX1XXLXLLXN
*V0139 XX0001010NX1XXLXLLXN
*V0140 XX0001011NX1XXLXLLXN
*V0141 XX0001100NX1XXLXLLXN
*V0142 XX0001101NX1XXLXLLXN
*V0143 XX0001110NX1XXLXLLXN
*V0144 XX0001111NX1XXLXLLXN
*V0145 XX0010000NX1XXLXXXXN
*V0146 XX0010001NX1XXLXXLXN
*V0147 XX0010010NX1XXLXLXXN
*V0148 XX0010011NX1XXLXLLXN
*V0149 XX0010100NX1XXLXLLXN
*V0150 XX0010101NX1XXLXLLXN
*V0151 XX0010110NX1XXLXLLXN
*V0152 XX0010111NX1XXLXLLXN
*V0153 XX0011000NX1XXLXLLXN
*V0154 XX0011001NX1XXLXLLXN
*V0155 XX0011010NX1XXLXLLXN
*V0156 XX0011011NX1XXLXLLXN
*V0157 XX0011100NX1XXLXLLXN
*V0158 XX0011101NX1XXLXLLXN
*V0159 XX0011110NX1XXLXLLXN
*V0160 XX0011111NX1XXLXLLXN
*V0161 XX0100000NX1XXLXLLXN
*V0162 XX0100001NX1XXLXLLXN
*V0163 XX0100010NX1XXLXLLXN
*V0164 XX0100011NX1XXLXLLXN
*V0165 XX0100100NX1XXLXLLXN
*V0166 XX0100101NX1XXLXLLXN
*V0167 XX0100110NX1XXLXLLXN
*V0168 XX0100111NX1XXLXLLXN
*V0169 XX0101000NX1XXLXLLXN
*V0170 XX0101001NX1XXLXLLXN
*V0171 XX0101010NX1XXLXLLXN
*V0172 XX0101011NX1XXLXLLXN
*V0173 XX0101100NX1XXLXLLXN
*V0174 XX0101101NX1XXLXLLXN
*V0175 XX0101110NX1XXLXLLXN
*V0176 XX0101111NX1XXLXLLXN
*V0177 XX0110000NX1XXLXLLXN
*V0178 XX0110001NX1XXLXLLXN
*V0179 XX0110010NX1XXLXLLXN
*V0180 XX0110011NX1XXLXLLXN
*V0181 XX0110100NX1XXLXLLXN
*V0182 XX0110101NX1XXLXLLXN
*V0183 XX0110110NX1XXLXLLXN
*V0184 XX0110111NX1XXLXLLXN
*V0185 XX0111000NX1XXLXLLXN
*V0186 XX0111001NX1XXLXLLXN
*V0187 XX0111010NX1XXLXLLXN
*V0188 XX0111011NX1XXLXLLXN
*V0189 XX0111100NX1XXLXLLXN
*V0190 XX0111101NX1XXLXLLXN
*V0191 XX0111110NX1XXLXLLXN
*V0192 XX0111111NX1XXLXLLXN
*V0193 XX1000000NX1XXLXLLXN
*V0194 XX1000001NX1XXLXLLXN
*V0195 XX1000010NX1XXLXLLXN
*V0196 XX1000011NX1XXLXLLXN
*V0197 XX1000100NX1XXLXLLXN
*V0198 XX1000101NX1XXLXLLXN
*V0199 XX1000110NX1XXLXLLXN
*V0200 XX1000111NX1XXLXLLXN
*V0201 XX1001000NX1XXLXLLXN
*V0202 XX1001001NX1XXLXLLXN
*V0203 XX1001010NX1XXLXLLXN
*V0204 XX1001011NX1XXLXLLXN
*V0205 XX1001100NX1XXLXLLXN
*V0206 XX1001101NX1XXLXLLXN
*V0207 XX1001110NX1XXLXLLXN
*V0208 XX1001111NX1XXLXLLXN
*V0209 XX1010000NX1XXLXLLXN
*V0210 XX1010001NX1XXLXLLXN
*V0211 XX1010010NX1XXLXLLXN
*V0212 XX1010011NX1XXLXLLXN
*V0213 XX1010100NX1XXLXLLXN
*V0214 XX1010101NX1XXLXLLXN
*V0215 XX1010110NX1XXLXLLXN
*V0216 XX1010111NX1XXLXLLXN
*V0217 XX1011000NX1XXLXLLXN
*V0218 XX1011001NX1XXLXLLXN
*V0219 XX1011010NX1XXLXLLXN
*V0220 XX1011011NX1XXLXLLXN
*V0221 XX1011100NX1XXLXLLXN
*V0222 XX1011101NX1XXLXLLXN
*V0223 XX1011110NX1XXLXLLXN
*V0224 XX1011111NX1XXLXLLXN
*V0225 XX1100000NX1XXLXLLXN
*V0226 XX1100001NX1XXLXLLXN
*V0227 XX1100010NX1XXLXLLXN
*V0228 XX1100011NX1XXLXLLXN
*V0229 XX1100100NX1XXLXLLXN
*V0230 XX1100101NX1XXLXLLXN
*V0231 XX1100110NX1XXLXLLXN
*V0232 XX1100111NX1XXLXLLXN
*V0233 XX1101000NX1XXLXLLXN
*V0234 XX1101001NX1XXLXLLXN
*V0235 XX1101010NX1XXLXLLXN
*V0236 XX1101011NX1XXLXLLXN
*V0237 XX1101100NX1XXLXLLXN
*V0238 XX1101101NX1XXLXLLXN
*V0239 XX1101110NX1XXLXLLXN
*V0240 XX1101111NX1XXLXLLXN
*V0241 XX1110000NX1XXLXLLXN
*V0242 XX1110001NX1XXLXLLXN
*V0243 XX1110010NX1XXLXLLXN
*V0244 XX1110011NX1XXLXLLXN
*V0245 XX1110100NX1XXLXLLXN
*V0246 XX1110101NX1XXLXLLXN
*V0247 XX1110110NX1XXLXLLXN
*V0248 XX1110111NX1XXLXLLXN
*V0249 XX1111000NX1XXLXLLXN
*V0250 XX1111001NX1XXLXLLXN
*V0251 XX1111010NX1XXLXLLXN
*V0252 XX1111011NX1XXLXLLXN
*V0253 XX1111100NX1XXLXLLXN
*V0254 XX1111101NX1XXLXLLXN
*V0255 XX1111110NX1XXLXLLXN
*V0256 XX1111111NX1XXLXLLXN
*V0257 0X1111111NX1XXLXLLHN
*V0258 1X1111111NX1XXLXLLLN
*V0259 0X1111111NX1XXLXLLLN
*V0260 1X1111111NX1XXLXLLHN
*V0261 0X1111111NX1XXLXLLHN
*V0262 1X1111111NX1XXLXLLLN
*V0263 0X1111111NX1XXLXLLLN
*V0264 1X1111111NX1XXLXLLHN
*V0265 0X1111111NX1XXLXLLHN
*V0266 1X1111111NX1XXLXLLLN
*V0267 0X1111111NX1XXLXLLLN
*V0268 1X1111111NX1XXLXLLHN
*V0269 0X1111111NX1XXLXLLHN
*V0270 1X1111111NX1XXLXLLLN
*V0271 0X1111111NX1XXLXLLLN
*V0272 1X1111111NX1XXLXLLHN
*V0273 0X1111111NX1XXLXLLHN
*V0274 1X1111111NX1XXLXLLLN
*V0275 0X1111111NX1XXLXLLLN
*V0276 1X1111111NX1XXLXLLHN
*V0277 0X1111111NX1XXLXLLHN
*V0278 1X1111111NX1XXLXLLLN
*V0279 0X1111111NX1XXLXLLLN
*V0280 1X1111111NX1XXLXLLHN
*V0281 0X1111111NX1XXLXLLHN
*V0282 1X1111111NX1XXLXLLLN
*V0283 0X1111111NX1XXLXLLLN
*V0284 1X1111111NX1XXLXLLHN
*V0285 0X1111111NX1XXLXLLHN
*V0286 1X1111111NX1XXLXLLLN
*V0287 0X1111111NX1XXLXLLLN
*V0288 1X1111111NX1XXLXLLHN
*V0289 0X1111111NX1XXLXLLHN
*V0290 1X1111111NX1XXLXLLLN
*V0291 0X1111111NX1XXLXLLLN
*V0292 1X1111111NX1XXLXLLHN
*V0293 0X1111111NX1XXLXLLHN
*V0294 1X1111111NX1XXLXLLLN
*V0295 0X1111111NX1XXLXLLLN
*V0296 1X1111111NX1XXLXLLHN
*V0297 0X1111111NX1XXLXLLHN
*34B9

187
trunk/workspace/01_CUPL/Z80_DEcoder_Paolo/Z80_DEC.pdf Normal file
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@@ -0,0 +1,187 @@
{COMPONENT Z:\VOLUMES\WALLET\WORK\WORKSPACE\01_CUPL\Z80_DECODER_PAOLO\Z80_DEC.SYM
{ENVIRONMENT
{PDIFvrev 3.00}
{Program "CUPL(WM) Version 5.0a"}
{DBtype "Schematic"}
{DBvrev 1.01}
{DBtime "Thu Nov 18 22:29:30 2021 "}
{DBunit "MIL"}
{DBgrid 10}
{Lyrstr "WIRES" 1 "BUS" 1 "GATE" 2 "IEEE" 2 "PINFUN" 3 "PINNUM" 1
"PINNAM" 6 "PINCON" 4 "REFDES" 2 "ATTR" 6 "SDOT" 1
"DEVICE" 5 "OUTLIN" 5 "ATTR2" 6 "NOTES" 6 "NETNAM" 4
"CMPNAM" 5 "BORDER" 5}
}
{USER
{VIEW
{Mode SYMB}
{Nlst OPEN}
{Vw 0 0 2}
{Lv 12 2 2 2 0 0 2 2 2 2 0 0 2 1 2 0 0 0 0}
{Gs 10 10}
}
}
{DISPLAY
[Ly "PINNUM"]
[Ls "SOLID"][Wd 0]
[Ts 15][Tj "LC"][Tr 0][Tm "N"]
}
{SYMBOL
{PIN_DEF
[Ly "PINCON"]
{P CLK_IN {Pt "INPUT"}{Lq 0}{Ploc 100 240}}
{P MREQ' {Pt "INPUT"}{Lq 0}{Ploc 100 200}}
{P IORQ' {Pt "INPUT"}{Lq 0}{Ploc 100 180}}
{P A7 {Pt "INPUT"}{Lq 0}{Ploc 100 160}}
{P A6 {Pt "INPUT"}{Lq 0}{Ploc 100 140}}
{P A5 {Pt "INPUT"}{Lq 0}{Ploc 100 120}}
{P A4 {Pt "INPUT"}{Lq 0}{Ploc 100 100}}
{P A0 {Pt "INPUT"}{Lq 0}{Ploc 100 80}}
{P WR' {Pt "INPUT"}{Lq 0}{Ploc 100 60}}
{P M1' {Pt "INPUT"}{Lq 0}{Ploc 100 40}}
{P CLK_OUT {Pt "INPUT"}{Lq 0}{Ploc 100 20}}
{P LCD_RS {Pt "I/O"}{Lq 0}{Ploc 350 20}}
{P LCD_RW {Pt "I/O"}{Lq 0}{Ploc 350 40}}
{P LCD_EN {Pt "I/O"}{Lq 0}{Ploc 350 60}}
{P PSG_BC1 {Pt "I/O"}{Lq 0}{Ploc 350 80}}
{P PSG_BDIR {Pt "I/O"}{Lq 0}{Ploc 350 100}}
}
{PKG
[Ly "REFDES"]
[Ts 25][Tj "CB"][Tr 0][Tm "N"]
{Rdl 225 270}
[Ly "PINNUM"]
[Ts 15][Tj "RC"]
{Pnl 120 250}
[Ts 15][Tj "RC"]
{Pnl 120 210}
{Pnl 120 190}
{Pnl 120 170}
{Pnl 120 150}
{Pnl 120 130}
{Pnl 120 110}
{Pnl 120 90}
{Pnl 120 70}
{Pnl 120 50}
{Pnl 120 30}
[Ts 15][Tj "LC"]
{Pnl 330 30}
{Pnl 330 50}
{Pnl 330 70}
{Pnl 330 90}
{Pnl 330 110}
{Sd A 1 2 3 4 5 6 7 8 9 12 19 13 14 15 17 18}
}
{PIC
[Ly "GATE"]
[Ts 15][Tj "LC"][Tr 0][Tm "N"]
{R 130 260 320 0}
{L 130 240 100 240}
{L 130 250 140 240 130 230}
{L 120 200 100 200}
{C 125 200 5}
{L 120 180 100 180}
{C 125 180 5}
{L 130 160 100 160}
{L 130 140 100 140}
{L 130 120 100 120}
{L 130 100 100 100}
{L 130 80 100 80}
{L 120 60 100 60}
{C 125 60 5}
{L 120 40 100 40}
{C 125 40 5}
{L 130 20 100 20}
{L 320 20 350 20}
{L 320 40 350 40}
{L 320 60 350 60}
{L 320 80 350 80}
{L 320 100 350 100}
[Ly "PINNAM"]
[Tj "LC"]
{T "CLK_IN" 140 240}
{T "MREQ'" 140 200}
{T "IORQ'" 140 180}
{T "A7" 140 160}
{T "A6" 140 140}
{T "A5" 140 120}
{T "A4" 140 100}
{T "A0" 140 80}
{T "WR'" 140 60}
{T "M1'" 140 40}
{T "CLK_OUT" 140 20}
[Tj "RC"]
{T "LCD_RS" 310 20}
{T "LCD_RW" 310 40}
{T "LCD_EN" 310 60}
{T "PSG_BC1" 310 80}
{T "PSG_BDIR" 310 100}
[Ly "DEVICE"]
[Tj "CT"]
{T "G16V8MS" 225 -10}
}
{ATR
{IN
{Org 100 20}
{Ty 255}
}
{EX
[Ly "ATTR2"]
[Ts 12][Tj "CT"][Tr 0][Tm "N"]
{At PLD Z:\VOLUMES\WALLET\WORK\WORKSPACE\01_CUPL\Z80_DECODER_PAOLO\Z80_DEC 225 260}
}
}
}
{DETAIL
{ANNOTATE
}
{NET_DEF
{N CLK_IN
}
{N MREQ'
}
{N IORQ'
}
{N A7
}
{N A6
}
{N A5
}
{N A4
}
{N A0
}
{N WR'
}
{N M1'
}
{N CLK_OUT
}
{N LCD_RS
}
{N LCD_RW
}
{N LCD_EN
}
{N PSG_BC1
}
{N PSG_BDIR
}
}
{SUBCOMP
}
}
}

69
trunk/workspace/01_CUPL/Z80_DEcoder_Paolo/Z80_DEC.pld Normal file
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Name Z80_DEC;
Partno g16v8;
Date 14/09/21;
Revision 00;
Designer Paolo Iocco;
Company GC73;
Assembly 00;
Location Munich;
Device G16V8;
/*
* Lattice GAL 16V8 pinout, DIP, top view
*
* CLK_IN-I/CLK.[ 1 20 ].VCC
* !MREQ - I.[ 2 19 ].I/O/Q - O CLK_OUT
* !IORQ - I.[ 3 18 ].I/O/Q - O PSG_BDIR
* A7 - I.[ 4 17 ].I/O/Q - O PSG_BC1
* A6 - I.[ 5 16 ].I/O/Q -
* A5 - I.[ 6 15 ].I/O/Q - O LCD_EN
* A4 - I.[ 7 14 ].I/O/Q - O LCD_RW
* A0 - I.[ 8 13 ].I/O/Q - O LCD_RS
* !WR - I.[ 9 12 ].I/O/Q - I !M1
* GND.[ 10 11 ].I -
*
*/
/* Inputs */
PIN 1 = CLK_IN;
PIN 2 = !MREQ;
PIN 3 = !IORQ;
PIN 4 = A7;
PIN 5 = A6;
PIN 6 = A5;
PIN 7 = A4;
PIN 8 = A0;
PIN 9 = !WR;
PIN 12 = !M1;
/* Outputs */
PIN 19 = CLK_OUT;
PIN 18 = PSG_BDIR;
PIN 17 = PSG_BC1;
//PIN 16 = !PSG_SEL;
PIN 15 = LCD_EN;
PIN 14 = LCD_RW;
PIN 13 = LCD_RS;
/* Rules */
/* WARNING! IORQ --> 1000xxx busy - Serial I/O) */
vPSG_SEL = !MREQ & IORQ & !A7 & A6 & !A5 & !A4; // b 0100xxxx base address $4x, IN(64+x), OUT(64+x)
vLCD = !MREQ & IORQ & !A7 & !A6 & !A5 & A4 & WR; // b 0001xxxx base address $1x, IN(16+x), OUT(16+x)
//vLCD = !M1 & IORQ & !A7 & !A6 & !A5 & A4 & WR; // b 0001xxxx base address $1x, IN(16+x), OUT(16+x)
vSpare = !MREQ & IORQ & !A7 & !A6 & A5 & !A4; // b 0010xxxx base address $2x, IN(32+x), OUT(32+x)
//vSpare = !M1 & IORQ & !A7 & !A6 & A5 & !A4; // b 0010xxxx base address $2x, IN(32+x), OUT(32+x)
PSG_SEL = vPSG_SEL;
PSG_BDIR = !(!vPSG_SEL # !WR);
PSG_BC1 = !(!vPSG_SEL # A0);
LCD_EN = vLCD;
LCD_RW = !WR;
LCD_RS = A0;
CLK_OUT.D = !CLK_OUT;

285
trunk/workspace/01_CUPL/Z80_DEcoder_Paolo/Z80_DEC.si Normal file
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Name Z80_DEC;
PartNo g16v8;
Date 14/09/21;
Revision 00;
Designer Paolo Iocco;
Company GC73;
Assembly 00;
Location Munich;
Device G16V8;
/* Logic Test */
/* ORDER: !MREQ, !IORQ, %1, A7, A6, A5, A4, %1, A0, %1, !WR, %4, !PSG_SEL, %2, PSG_BDIR, %2, PSG_BC1; */
ORDER: !M1, !IORQ, %1, A7, A6, A5, A4, %1, A0, %1, !WR, %4, PSG_BDIR, %2, PSG_BC1, %2, LCD_EN;
/* ---------- */
VECTORS:
00000000 ***
00000001 ***
00000010 ***
00000011 ***
00000100 ***
00000101 ***
00000110 ***
00000111 ***
00001000 ***
00001001 ***
00001010 ***
00001011 ***
00001100 ***
00001101 ***
00001110 ***
00001111 ***
00010000 ***
00010001 ***
00010010 ***
00010011 ***
00010100 ***
00010101 ***
00010110 ***
00010111 ***
00011000 ***
00011001 ***
00011010 ***
00011011 ***
00011100 ***
00011101 ***
00011110 ***
00011111 ***
00100000 ***
00100001 ***
00100010 ***
00100011 ***
00100100 ***
00100101 ***
00100110 ***
00100111 ***
00101000 ***
00101001 ***
00101010 ***
00101011 ***
00101100 ***
00101101 ***
00101110 ***
00101111 ***
00110000 ***
00110001 ***
00110010 ***
00110011 ***
00110100 ***
00110101 ***
00110110 ***
00110111 ***
00111000 ***
00111001 ***
00111010 ***
00111011 ***
00111100 ***
00111101 ***
00111110 ***
00111111 ***
01000000 ***
01000001 ***
01000010 ***
01000011 ***
01000100 ***
01000101 ***
01000110 ***
01000111 ***
01001000 ***
01001001 ***
01001010 ***
01001011 ***
01001100 ***
01001101 ***
01001110 ***
01001111 ***
01010000 ***
01010001 ***
01010010 ***
01010011 ***
01010100 ***
01010101 ***
01010110 ***
01010111 ***
01011000 ***
01011001 ***
01011010 ***
01011011 ***
01011100 ***
01011101 ***
01011110 ***
01011111 ***
01100000 ***
01100001 ***
01100010 ***
01100011 ***
01100100 ***
01100101 ***
01100110 ***
01100111 ***
01101000 ***
01101001 ***
01101010 ***
01101011 ***
01101100 ***
01101101 ***
01101110 ***
01101111 ***
01110000 ***
01110001 ***
01110010 ***
01110011 ***
01110100 ***
01110101 ***
01110110 ***
01110111 ***
01111000 ***
01111001 ***
01111010 ***
01111011 ***
01111100 ***
01111101 ***
01111110 ***
01111111 ***
10000000 ***
10000001 ***
10000010 ***
10000011 ***
10000100 ***
10000101 ***
10000110 ***
10000111 ***
10001000 ***
10001001 ***
10001010 ***
10001011 ***
10001100 ***
10001101 ***
10001110 ***
10001111 ***
10010000 ***
10010001 ***
10010010 ***
10010011 ***
10010100 ***
10010101 ***
10010110 ***
10010111 ***
10011000 ***
10011001 ***
10011010 ***
10011011 ***
10011100 ***
10011101 ***
10011110 ***
10011111 ***
10100000 ***
10100001 ***
10100010 ***
10100011 ***
10100100 ***
10100101 ***
10100110 ***
10100111 ***
10101000 ***
10101001 ***
10101010 ***
10101011 ***
10101100 ***
10101101 ***
10101110 ***
10101111 ***
10110000 ***
10110001 ***
10110010 ***
10110011 ***
10110100 ***
10110101 ***
10110110 ***
10110111 ***
10111000 ***
10111001 ***
10111010 ***
10111011 ***
10111100 ***
10111101 ***
10111110 ***
10111111 ***
11000000 ***
11000001 ***
11000010 ***
11000011 ***
11000100 ***
11000101 ***
11000110 ***
11000111 ***
11001000 ***
11001001 ***
11001010 ***
11001011 ***
11001100 ***
11001101 ***
11001110 ***
11001111 ***
11010000 ***
11010001 ***
11010010 ***
11010011 ***
11010100 ***
11010101 ***
11010110 ***
11010111 ***
11011000 ***
11011001 ***
11011010 ***
11011011 ***
11011100 ***
11011101 ***
11011110 ***
11011111 ***
11100000 ***
11100001 ***
11100010 ***
11100011 ***
11100100 ***
11100101 ***
11100110 ***
11100111 ***
11101000 ***
11101001 ***
11101010 ***
11101011 ***
11101100 ***
11101101 ***
11101110 ***
11101111 ***
11110000 ***
11110001 ***
11110010 ***
11110011 ***
11110100 ***
11110101 ***
11110110 ***
11110111 ***
11111000 ***
11111001 ***
11111010 ***
11111011 ***
11111100 ***
11111101 ***
11111110 ***
11111111 ***
/* Clock divider test */
ORDER: CLK_IN, %3, CLK_OUT;
/* ------------------ */
VECTORS:
0*
$FOR i = 1..20:
1*
0*
$ENDF;

81
trunk/workspace/01_CUPL/Z80_DEcoder_Paolo/Z80_DEC.sim Normal file
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@@ -0,0 +1,81 @@
%SIGNAL
PIN 8 = A0
PIN 7 = A4
PIN 6 = A5
PIN 5 = A6
PIN 4 = A7
PIN 1 = CLK_IN
PIN 19 = CLK_OUT
PIN 3 = !IORQ
PIN 15 = LCD_EN
PIN 13 = LCD_RS
PIN 14 = LCD_RW
PIN 12 = !M1
PIN 2 = !MREQ
PIN 17 = PSG_BC1
PIN 18 = PSG_BDIR
PIN 9 = !WR
%END
%FIELD
%END
%EQUATION
CLK_OUT.d =>
!CLK_OUT
LCD_EN =>
A4 & !A5 & !A6 & !A7 & !IORQ & MREQ & !WR
LCD_RS =>
A0
LCD_RW =>
WR
PSG_BC1 =>
!MREQ
# IORQ
# A7
# !A6
# A5
# A4
# A0
PSG_BDIR =>
!MREQ
# IORQ
# A7
# !A6
# A5
# A4
# WR
PSG_SEL =>
!A4 & !A5 & A6 & !A7 & IORQ & !MREQ
vLCD =>
A4 & !A5 & !A6 & !A7 & IORQ & !MREQ & WR
vPSG_SEL =>
!A4 & !A5 & A6 & !A7 & IORQ & !MREQ
vSpare =>
!A4 & A5 & !A6 & !A7 & IORQ & !MREQ
LCD_EN.oe =>
1
LCD_RS.oe =>
1
LCD_RW.oe =>
1
PSG_BC1.oe =>
1
PSG_BDIR.oe =>
1
%END

316
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#WAVEFORM
#H Name Z80_DEC;
#H PartNo g16v8;
#H Date 14/09/21;
#H Revision 00;
#H Designer Paolo Iocco;
#H Company GC73;
#H Assembly 00;
#H Location Munich;
#H Device G16V8;
#H
#H /* Logic Test */
#H /* ORDER: !MREQ, !IORQ, %1, A7, A6, A5, A4, %1, A0, %1, !WR, %4, !PSG_SEL, %2, PSG_BDIR, %2, PSG_BC1; */
#H ORDER: !M1, !IORQ, %1, A7, A6, A5, A4, %1, A0, %1, !WR, %4, PSG_BDIR, %2, PSG_BC1, %2, LCD_EN;
#H
#H /* ---------- */
#V 0001 00000000LLL
#V 0002 00000001LLL
#V 0003 00000010LLL
#V 0004 00000011LLL
#V 0005 00000100LLX
#V 0006 00000101LLL
#V 0007 00000110LLX
#V 0008 00000111LLL
#V 0009 00001000LLL
#V 0010 00001001LLL
#V 0011 00001010LLL
#V 0012 00001011LLL
#V 0013 00001100LLL
#V 0014 00001101LLL
#V 0015 00001110LLL
#V 0016 00001111LLL
#V 0017 00010000XXL
#V 0018 00010001LXL
#V 0019 00010010XLL
#V 0020 00010011LLL
#V 0021 00010100LLL
#V 0022 00010101LLL
#V 0023 00010110LLL
#V 0024 00010111LLL
#V 0025 00011000LLL
#V 0026 00011001LLL
#V 0027 00011010LLL
#V 0028 00011011LLL
#V 0029 00011100LLL
#V 0030 00011101LLL
#V 0031 00011110LLL
#V 0032 00011111LLL
#V 0033 00100000LLL
#V 0034 00100001LLL
#V 0035 00100010LLL
#V 0036 00100011LLL
#V 0037 00100100LLL
#V 0038 00100101LLL
#V 0039 00100110LLL
#V 0040 00100111LLL
#V 0041 00101000LLL
#V 0042 00101001LLL
#V 0043 00101010LLL
#V 0044 00101011LLL
#V 0045 00101100LLL
#V 0046 00101101LLL
#V 0047 00101110LLL
#V 0048 00101111LLL
#V 0049 00110000LLL
#V 0050 00110001LLL
#V 0051 00110010LLL
#V 0052 00110011LLL
#V 0053 00110100LLL
#V 0054 00110101LLL
#V 0055 00110110LLL
#V 0056 00110111LLL
#V 0057 00111000LLL
#V 0058 00111001LLL
#V 0059 00111010LLL
#V 0060 00111011LLL
#V 0061 00111100LLL
#V 0062 00111101LLL
#V 0063 00111110LLL
#V 0064 00111111LLL
#V 0065 01000000LLL
#V 0066 01000001LLL
#V 0067 01000010LLL
#V 0068 01000011LLL
#V 0069 01000100LLL
#V 0070 01000101LLL
#V 0071 01000110LLL
#V 0072 01000111LLL
#V 0073 01001000LLL
#V 0074 01001001LLL
#V 0075 01001010LLL
#V 0076 01001011LLL
#V 0077 01001100LLL
#V 0078 01001101LLL
#V 0079 01001110LLL
#V 0080 01001111LLL
#V 0081 01010000LLL
#V 0082 01010001LLL
#V 0083 01010010LLL
#V 0084 01010011LLL
#V 0085 01010100LLL
#V 0086 01010101LLL
#V 0087 01010110LLL
#V 0088 01010111LLL
#V 0089 01011000LLL
#V 0090 01011001LLL
#V 0091 01011010LLL
#V 0092 01011011LLL
#V 0093 01011100LLL
#V 0094 01011101LLL
#V 0095 01011110LLL
#V 0096 01011111LLL
#V 0097 01100000LLL
#V 0098 01100001LLL
#V 0099 01100010LLL
#V 0100 01100011LLL
#V 0101 01100100LLL
#V 0102 01100101LLL
#V 0103 01100110LLL
#V 0104 01100111LLL
#V 0105 01101000LLL
#V 0106 01101001LLL
#V 0107 01101010LLL
#V 0108 01101011LLL
#V 0109 01101100LLL
#V 0110 01101101LLL
#V 0111 01101110LLL
#V 0112 01101111LLL
#V 0113 01110000LLL
#V 0114 01110001LLL
#V 0115 01110010LLL
#V 0116 01110011LLL
#V 0117 01110100LLL
#V 0118 01110101LLL
#V 0119 01110110LLL
#V 0120 01110111LLL
#V 0121 01111000LLL
#V 0122 01111001LLL
#V 0123 01111010LLL
#V 0124 01111011LLL
#V 0125 01111100LLL
#V 0126 01111101LLL
#V 0127 01111110LLL
#V 0128 01111111LLL
#V 0129 10000000LLL
#V 0130 10000001LLL
#V 0131 10000010LLL
#V 0132 10000011LLL
#V 0133 10000100LLX
#V 0134 10000101LLL
#V 0135 10000110LLX
#V 0136 10000111LLL
#V 0137 10001000LLL
#V 0138 10001001LLL
#V 0139 10001010LLL
#V 0140 10001011LLL
#V 0141 10001100LLL
#V 0142 10001101LLL
#V 0143 10001110LLL
#V 0144 10001111LLL
#V 0145 10010000XXL
#V 0146 10010001LXL
#V 0147 10010010XLL
#V 0148 10010011LLL
#V 0149 10010100LLL
#V 0150 10010101LLL
#V 0151 10010110LLL
#V 0152 10010111LLL
#V 0153 10011000LLL
#V 0154 10011001LLL
#V 0155 10011010LLL
#V 0156 10011011LLL
#V 0157 10011100LLL
#V 0158 10011101LLL
#V 0159 10011110LLL
#V 0160 10011111LLL
#V 0161 10100000LLL
#V 0162 10100001LLL
#V 0163 10100010LLL
#V 0164 10100011LLL
#V 0165 10100100LLL
#V 0166 10100101LLL
#V 0167 10100110LLL
#V 0168 10100111LLL
#V 0169 10101000LLL
#V 0170 10101001LLL
#V 0171 10101010LLL
#V 0172 10101011LLL
#V 0173 10101100LLL
#V 0174 10101101LLL
#V 0175 10101110LLL
#V 0176 10101111LLL
#V 0177 10110000LLL
#V 0178 10110001LLL
#V 0179 10110010LLL
#V 0180 10110011LLL
#V 0181 10110100LLL
#V 0182 10110101LLL
#V 0183 10110110LLL
#V 0184 10110111LLL
#V 0185 10111000LLL
#V 0186 10111001LLL
#V 0187 10111010LLL
#V 0188 10111011LLL
#V 0189 10111100LLL
#V 0190 10111101LLL
#V 0191 10111110LLL
#V 0192 10111111LLL
#V 0193 11000000LLL
#V 0194 11000001LLL
#V 0195 11000010LLL
#V 0196 11000011LLL
#V 0197 11000100LLL
#V 0198 11000101LLL
#V 0199 11000110LLL
#V 0200 11000111LLL
#V 0201 11001000LLL
#V 0202 11001001LLL
#V 0203 11001010LLL
#V 0204 11001011LLL
#V 0205 11001100LLL
#V 0206 11001101LLL
#V 0207 11001110LLL
#V 0208 11001111LLL
#V 0209 11010000LLL
#V 0210 11010001LLL
#V 0211 11010010LLL
#V 0212 11010011LLL
#V 0213 11010100LLL
#V 0214 11010101LLL
#V 0215 11010110LLL
#V 0216 11010111LLL
#V 0217 11011000LLL
#V 0218 11011001LLL
#V 0219 11011010LLL
#V 0220 11011011LLL
#V 0221 11011100LLL
#V 0222 11011101LLL
#V 0223 11011110LLL
#V 0224 11011111LLL
#V 0225 11100000LLL
#V 0226 11100001LLL
#V 0227 11100010LLL
#V 0228 11100011LLL
#V 0229 11100100LLL
#V 0230 11100101LLL
#V 0231 11100110LLL
#V 0232 11100111LLL
#V 0233 11101000LLL
#V 0234 11101001LLL
#V 0235 11101010LLL
#V 0236 11101011LLL
#V 0237 11101100LLL
#V 0238 11101101LLL
#V 0239 11101110LLL
#V 0240 11101111LLL
#V 0241 11110000LLL
#V 0242 11110001LLL
#V 0243 11110010LLL
#V 0244 11110011LLL
#V 0245 11110100LLL
#V 0246 11110101LLL
#V 0247 11110110LLL
#V 0248 11110111LLL
#V 0249 11111000LLL
#V 0250 11111001LLL
#V 0251 11111010LLL
#V 0252 11111011LLL
#V 0253 11111100LLL
#V 0254 11111101LLL
#V 0255 11111110LLL
#V 0256 11111111LLL
#H ORDER: CLK_IN, %3, CLK_OUT;
#H
#H /* ------------------ */
#V 0257 0H
#V 0258 1L
#V 0259 0L
#V 0260 1H
#V 0261 0H
#V 0262 1L
#V 0263 0L
#V 0264 1H
#V 0265 0H
#V 0266 1L
#V 0267 0L
#V 0268 1H
#V 0269 0H
#V 0270 1L
#V 0271 0L
#V 0272 1H
#V 0273 0H
#V 0274 1L
#V 0275 0L
#V 0276 1H
#V 0277 0H
#V 0278 1L
#V 0279 0L
#V 0280 1H
#V 0281 0H
#V 0282 1L
#V 0283 0L
#V 0284 1H
#V 0285 0H
#V 0286 1L
#V 0287 0L
#V 0288 1H
#V 0289 0H
#V 0290 1L
#V 0291 0L
#V 0292 1H
#V 0293 0H
#V 0294 1L
#V 0295 0L
#V 0296 1H
#V 0297 0H

60
trunk/workspace/01_CUPL/Z80_Decoder/Z80_DEC.doc Normal file
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*******************************************************************************
Z80_Dec
*******************************************************************************
CUPL(WM) 5.0a Serial# 60008009
Device g16v8s Library DLIB-h-40-9
Created Tue Apr 25 11:46:07 2017
Name Z80_Dec
Partno g16v8
Revision 00
Date 25/04/17
Designer Paolo Iocco
Company GC73
Assembly 00
Location Munich
===============================================================================
Expanded Product Terms
===============================================================================
!EPROM =>
!A13 & !A14 & !A15 & !MREQ
!IO0 =>
!A6 & !A7 & !IOREQ
!IO1 =>
A6 & !A7 & !IOREQ
!RAM =>
A13 & !A14 & !A15 & !MREQ
===============================================================================
Symbol Table
===============================================================================
Pin Variable Pterms Max Min
Pol Name Ext Pin Type Used Pterms Level
--- -------- --- --- ---- ------ ------ -----
A6 6 V - - -
A7 5 V - - -
A13 4 V - - -
A14 3 V - - -
A15 2 V - - -
EPROM 19 V 1 8 1
IO0 17 V 1 8 1
IO1 16 V 1 8 1
! IOREQ 8 V - - -
! MREQ 7 V - - -
RAM 18 V 1 8 1
LEGEND D : default variable F : field G : group
I : intermediate variable N : node M : extended node
U : undefined V : variable X : extended variable
T : function

108
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{COMPONENT H:\WORKSPACE\01_CUPL\Z80_DECODER\Z80_DEC.SYM
{ENVIRONMENT
{PDIFvrev 3.00}
{Program "CUPL(WM) Version 5.0a"}
{DBtype "Schematic"}
{DBvrev 1.01}
{DBtime "Mon Dec 07 23:08:19 2020 "}
{DBunit "MIL"}
{DBgrid 10}
{Lyrstr "WIRES" 1 "BUS" 1 "GATE" 2 "IEEE" 2 "PINFUN" 3 "PINNUM" 1
"PINNAM" 6 "PINCON" 4 "REFDES" 2 "ATTR" 6 "SDOT" 1
"DEVICE" 5 "OUTLIN" 5 "ATTR2" 6 "NOTES" 6 "NETNAM" 4
"CMPNAM" 5 "BORDER" 5}
}
{USER
{VIEW
{Mode SYMB}
{Nlst OPEN}
{Vw 0 0 2}
{Lv 12 2 2 2 0 0 2 2 2 2 0 0 2 1 2 0 0 0 0}
{Gs 10 10}
}
}
{DISPLAY
[Ly "PINNUM"]
[Ls "SOLID"][Wd 0]
[Ts 15][Tj "LC"][Tr 0][Tm "N"]
}
{SYMBOL
{PIN_DEF
[Ly "PINCON"]
{P IO1 {Pt "I/O"}{Lq 0}{Ploc 280 20}}
{P IO0 {Pt "I/O"}{Lq 0}{Ploc 280 40}}
{P RAM {Pt "I/O"}{Lq 0}{Ploc 280 60}}
{P EPROM {Pt "I/O"}{Lq 0}{Ploc 280 80}}
}
{PKG
[Ly "REFDES"]
[Ts 25][Tj "CB"][Tr 0][Tm "N"]
{Rdl 190 110}
[Ly "PINNUM"]
[Ts 15][Tj "LC"]
{Pnl 260 30}
{Pnl 260 50}
{Pnl 260 70}
{Pnl 260 90}
{Sd A 16 17 18 19}
}
{PIC
[Ly "GATE"]
[Ts 15][Tj "LC"][Tr 0][Tm "N"]
{R 130 100 250 0}
{L 250 20 280 20}
{L 250 40 280 40}
{L 250 60 280 60}
{L 250 80 280 80}
[Ly "PINNAM"]
[Tj "LC"]
[Tj "RC"]
{T "IO1" 240 20}
{T "IO0" 240 40}
{T "RAM" 240 60}
{T "EPROM" 240 80}
[Ly "DEVICE"]
[Tj "CT"]
{T "VIRTUAL" 190 -10}
}
{ATR
{IN
{Org 100 20}
{Ty 255}
}
{EX
[Ly "ATTR2"]
[Ts 12][Tj "CT"][Tr 0][Tm "N"]
{At PLD H:\WORKSPACE\01_CUPL\Z80_DECODER\Z80_DEC 190 100}
}
}
}
{DETAIL
{ANNOTATE
}
{NET_DEF
{N IO1
}
{N IO0
}
{N RAM
}
{N EPROM
}
}
{SUBCOMP
}
}
}

31
trunk/workspace/01_CUPL/Z80_Decoder/Z80_DEC.si Normal file
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Name Z80_Dec;
PartNo g16v8;
Date 25/04/17;
Revision 00;
Designer Paolo Iocco;
Company GC73;
Assembly 00;
Location Munich;
Device G16V8;
ORDER: MREQ, A15, A14, A13, EPROM, RAM, IOREQ, A7, A6, IO0, IO1;
VECTORS:
0000**000**
0001**001**
0010**010**
0011**011**
0100**100**
0101**101**
0110**110**
0111**111**
1000**000**
1001**001**
1010**010**
1011**011**
1100**100**
1101**101**
1110**110**
1111**111**

45
trunk/workspace/01_CUPL/Z80_Decoder/Z80_Dec.jed Normal file
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CUPL(WM) 5.0a Serial# 60008009
Device g16v8s Library DLIB-h-40-9
Created Tue Apr 25 15:09:40 2017
Name Z80_Dec
Partno g16v8
Revision 00
Date 25/04/17
Designer Paolo Iocco
Company GC73
Assembly 00
Location Munich
*QP20
*QF2194
*QV16
*G0
*F0
*L00000 10111011101111111111011111111111
*L00256 10111011011111111111011111111111
*L00512 11111111111110111011111101111111
*L00768 11111111111110110111111101111111
*L02048 00000000011001110011000100110110
*L02080 01110110001110000000000000000000
*L02112 00000000000011111111111111111111
*L02144 11111111111111111111111111111111
*L02176 111111111111111110
*C1A95
*P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
*V0001 X0000011XNXXXXXHLHLN
*V0002 X0010111XNXXXXXLHLHN
*V0003 X0101011XNXXXXXHHHHN
*V0004 X0111111XNXXXXXHHHHN
*V0005 X1000010XNXXXXXHHHHN
*V0006 X1010110XNXXXXXHHHHN
*V0007 X1101010XNXXXXXHHHHN
*V0008 X1111110XNXXXXXHHHHN
*V0009 X0000001XNXXXXXHLHHN
*V0010 X0010101XNXXXXXLHHHN
*V0011 X0101001XNXXXXXHHHHN
*V0012 X0111101XNXXXXXHHHHN
*V0013 X1000000XNXXXXXHHHHN
*V0014 X1010100XNXXXXXHHHHN
*V0015 X1101000XNXXXXXHHHHN
*V0016 X1111100XNXXXXXHHHHN
*0DE4

42
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Name Z80_Dec;
Partno g16v8;
Date 25/04/17;
Revision 00;
Designer Paolo Iocco;
Company GC73;
Assembly 00;
Location Munich;
Device G16V8;
/* ****************************** */
/* Z80 memory and I/O decoder */
/* Memory Map */
/* 0000-1FFF EPROM */
/* 2000-3FFF RAM */
/* xxx IO0 */
/* yyy IO1 */
/* ****************************** */
/** Inputs **/
pin 2 = A15;
pin 3 = A14;
pin 4 = A13;
pin 5 = A7;
pin 6 = A6;
pin 7 = !MREQ;
pin 8 = !IOREQ;
/** Outputs **/
pin 19 = EPROM;
pin 18 = RAM;
pin 17 = IO0;
pin 16 = IO1;
/** Logic Equations **/
!EPROM = !A15 & !A14 & !A13 & !MREQ ;
!RAM = !A15 & !A14 & A13 & !MREQ ;
!IO0 = !A7 & !A6 & !IOREQ ;
!IO1 = !A7 & A6 & !IOREQ ;

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@echo off
rem
rem The arguments expected by this batch file are:
rem
rem %1 - source file name (without the .ABL extension)
rem %2-%4 - AHDL2PLA, PLAOPT, FUSEASM or JEDSIM options
rem
rem Additional command line options for ABEL programs may be
rem specified either in the ABEL-HDL source file (in an OPTIONS
rem statement) or in the ABELBAT2.BAT file.
rem
SET ABEL4DEV=E:\0_WORK~1\01_EAS~1\LIB4
SET ABEL4DB=E:\0_WORK~1\01_EAS~1\LIB4\DEVICES
SET DB_DICT=E:\0_WORK~1\01_EAS~1\LIB4\DBASE
PATH E:\0_WORK~1\01_EAS~1;%PATH%
if "%1" == "" goto error
if not exist %1.abl goto error1
if not "%5" == "" echo Warning: too many arguments - %5 ignored.
if not "%6" == "" echo Warning: too many arguments - %6 ignored.
if not "%7" == "" echo Warning: too many arguments - %7 ignored.
if not "%8" == "" echo Warning: too many arguments - %8 ignored.
if not "%9" == "" echo Warning: too many arguments - %9 ignored.
echo ABEL Batch Utility - Copyright (c) 1990 Data I/O Corp. All Rights Reserved
ahdl2pla %1 -list -batch %2 %3 %4
if errorlevel == 1 goto end
command /c %1.bat %2 %3 %4
del %1.bat
goto end
:error
echo Usage: abel4bat abel_file [option1 option2 option3]
goto end
:error1
echo Could not find input file "%1.abl"
:end

31
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@echo off
rem
rem The arguments expected by this batch file are:
rem
rem %1 - source file name (without the .ABL extension)
rem %2-%4 - AHDL2PLA, PLAOPT, FUSEASM or JEDSIM options
rem
rem Additional command line options for ABEL programs may be
rem specified either in the ABEL-HDL source file (in an OPTIONS
rem statement) or in the ABELBAT2.BAT file.
rem
if "%1" == "" goto error
if not exist %1.abl goto error1
if not "%5" == "" echo Warning: too many arguments - %5 ignored.
if not "%6" == "" echo Warning: too many arguments - %6 ignored.
if not "%7" == "" echo Warning: too many arguments - %7 ignored.
if not "%8" == "" echo Warning: too many arguments - %8 ignored.
if not "%9" == "" echo Warning: too many arguments - %9 ignored.
echo ABEL Batch Utility - Copyright (c) 1990 Data I/O Corp. All Rights Reserved
ahdl2pla %1 -list -batch %2 %3 %4
if errorlevel == 1 goto end
command /c %1.bat %2 %3 %4
del %1.bat
goto end
:error
echo Usage: abel4bat abel_file [option1 option2 option3]
goto end
:error1
echo Could not find input file "%1.abl"
:end

18
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@echo off
rem
rem The arguments expected by this batch file are:
rem
rem %1 - The ABEL-PLA root file name (with no .TT1 extension)
rem %2 - The JEDEC file name
rem %3-%9 - PLAOPT, FUSEASM or JEDSIM options
rem
rem Default options for PLAOPT, FUSEASM or JEDSIM can be specified
rem after the first argument to each program as shown for PLAOPT
rem and FUSEASM below.
rem
plaopt %1.tt1 %3 %4 %5 %6 %7 %8 %9
if errorlevel == 1 goto end
fuseasm %1.tt2 %3 %4 %5 %6 %7 %8 %9
if errorlevel == 1 goto end
jedsim %2.jed %3 %4 %5 %6 %7 %8 %9
:end

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*Comment
$Header: /swpg/develop/abel/xlport/ade/RCS/abelmenu.mnu,v 9.18.2.1 1991/10/29 00:04:31 peterson Exp $
*Version
4
*Header
Data I/O easyABEL Design Environment
*Welcome
easyABEL Design Environment
easyABEL Release 4.30 Copyright 1992 Data I/O Corp. All Rights Reserved
Vermont Views Library Software, Version 2.0
Copyright 1988,1990 Vermont Creative Software
easyABEL is NOT a free product.
It is Shareware and users who use it regularly must register it.
This is an unregistered copy of the easyABEL Design Environment.
To register, send DM 390,- (+15% MwSt.) to:
Data I/O GmbH
Lochhamer Schlag 5
W-8032 Graefelfing
Tel.: 089/85858-0
Registered users will receive a user licence
and a complete easyABEL manual
*ErrorMsg
/* 00 */ "Unknown error",
/* 01 */ "Can't find \"%s\" section in menu definition file\n",
/* 02 */ "Row length of %s section is defined incorrectly: %d!=%d\n",
/* 03 */ "String \"%s\" in section \"%s\" too long for menu: strlen > %d\n",
/* 04 */ "Can't find %s\n",
/* 05 */ "Couldn't insert Form(%d:%d) in menu tree\n",
/* 06 */ "Couldn't find sub-menu %d\n",
/* 07 */ "Couldn't change radio-button %s to %c\n",
/* 08 */ "Error updating radio-button field %s\n",
/* 09 */ "Out of memory",
/* 10 */ "Couldn't lookup extension %d in depend list\n",
/* 11 */ "Error while reading file \"%s\"",
/* 12 */ "Couldn't find/open file \"%s\"",
/* 13 */ "File \"%s\" is empty",
/* 14 */ "Couldn't save options to file \"%s\"",
/* 15 */ "Unable to find section \"%s\" in menu definition file",
/* 16 */ "Couldn't write file \"%s\"",
/* 17 */ "Incorrect version of abelmenu.mnu. Should be \"%s\".\nUsed file \"%s\" as menu definition file.",
/* 18 */ "Couldn't install interrupt handler for %s.",
*GenericMsg
/* 00 */ "Press any key to continue",
/* 01 */ "Display: %s (<<ESC>> to quit)",
/* 02 */ "Error occurred: ",
/* 03 */ "Line(s) too long.",
/* 04 */ "One line deleted",
/* 05 */ "One line replicated",
/* 06 */ "Couldn't find text \"%s\"",
/* 07 */ "File \"%s\" sent to printer",
/* 08 */ "Incorrect range specification. Press <<F1>> for help.",
/* 09 */ "Available Memory = %dkb",
/* 10 */ "%s successfully completed.",
/* 11 */ "Updating %s pass.",
/* 12 */ "Running %s.",
/* 13 */ "Done with %s. <<ESC>> to edit.",
/* 14 */ "Error during %s. Use View-Error. <<ESC>> to edit.",
/* 15 */ "Error during %s update. Use View-Error. <<ESC>> to edit.",
/* 16 */ "Paused: ",
/* 17 */ "Press <<F1>> for Help. <<ESC>> <<_AltLetter_>>for menu.",
/* 18 */ "< Yes >",
/* 19 */ "< No >",
/* 20 */ "Press <<F2>> for list, <<F6>> to clear list",
/* 21 */ "Loading Help. Please wait...",
/* 22 */ "Press space bar to toggle check box",
/* 23 */ "Press space bar to select item",
/* 24 */ "Type in data",
/* 25 */ "Press Enter to perform button action",
/* 26 */ "Enter in range data of the form #, < #, > #, or #-#",
/* 27 */ "Disabling auto-update for non ABEL-HDL file",
/* 28 */ "No \"Device List File\" specified: please specify file",
/* 29 */ "Choose from list. Press Enter when done",
/* 30 */ "No choice list found - enter data directly",
/* 31 */ "Function not supported yet",
/* 32 */ "Press <<F2>> for SmartPart Device Selector generated list",
/* 33 */ "Press <<F2>> for Fitter generated list",
/* 34 */ "No device specified in source or on Fitter Options dialog box.\n Can't continue without a device.",
/* 35 */ " Simulate Optimized ", /* This must not change length */
/* 36 */ "Simulate the optimized equations",
/* 37 */ "Type \"exit\" to return to abel4.\n",
/* 38 */ " Help ",
/* 39 */ "Choose a sub-topic and press enter.",
/* 40 */ "Press <<F2>> for list of Module names",
/* 41 */ "Error occurred during processing flow for file \"%s\".",
/* 42 */ "Error occurred during processing flow for file \"%s\".\nFile is out of date.",
/* 43 */ "Help menu \"%s\" not found.",
/* 44 */ "Press <<F1>> for Help",
/* 45 */ "Not enough memory to load file \"%s\".",
/* 46 */ "Unloading Help to gain more free memory.",
/* 47 */ "Error making backup (.sav). Disk may be full.",
/* 48 */ "<<OS>> error during program execution. Please Save&Exit.",
/* 49 */ "Not enough space to swap ABEL4 to disk. Couldn't run requested program.",
/* 50 */ "Error: program couldn't execute.",
/* 51 */ "Couldn't find JEDEC file \"%s\".",
/* 52 */ "Loading file \"%s\"...",
/* 53 */ "Copied file \"%s\" to \"%s\".",
/* 54 */ "Choose from list. Space bar to select, press Enter when done",
/* 55 */ "Can't find file \"%s\"",
/* 56 */ "Error reading help file",
/* 57 */ "Insufficient memory to perform requested task",
/* 58 */ "Press Return key to continue",
/* 59 */ "Appending to batch file \"%s\"",
/* 60 */ "Editor is in read only mode",
/* 61 */ "Could not write to file \"%s\"",
/* 62 */ "Saved file as \"%s\"",
/* 63 */ "ABEL Serial Number: ",
/* 64 */ "%s environment variable not set",
/* 65 */ "Directory \"%s\" not found",
/* 66 */ " FPGA/PLDmap ",
/* 67 */ " \"%s\" was renamed \"%s\".\nPlease see the User Notes on the file\nname change of the .opt file to .aop",
/* 68 */ " Couldn't rename file \"%s\" to \"%s\".\nPlease see the User Notes on the file\nname change to the .opt file to .aop",
*Comment
1 1 2 2 3 3 4 4 5 5 6 6 7 7
0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5
File Edit View Compile Optimize SmartPart PartMap Xfer Defaults Help
File Edit View Compile Optimize SmartPart PartMap Defaults Help
File Edit View Compile Optimize Select/Fit Map Defaults Help
File Edit View Compile Optimize Select/Fit Map Utilities Defaults Help
*Top Menu
0 0 1 -1
0 0 1 " File "
0 6 1 " Edit "
0 12 1 " View "
0 18 1 " Compile "
0 27 1 " Optimize "
0 37 1 " SmartPart "
0 48 1 " PartMap "
0 57 1 " Xfer "
0 64 1 " Defaults "
0 -7 1 " Help "
*File Menu
1 0 13 17
$BOX
1 1 1 " New " "Clear the current design"
2 1 1 " Open... " "Open and read a design file"
3 1 1 " Merge... " "Merge file into current file"
4 1 1 " Save " "Write the current design"
5 1 6 " Save As... " "Save the current design with a new name"
$LINE
7 1 1 " Print... " "Send a file to the printer"
8 1 1 " <<OSSHELL>> " "Temporarily exit to a <<OSSHELL>>"
$LINE
10 1 10 " Save and Exit " "Save file and exit the ABEL Design Environment"
11 1 2 " Exit " "Exit the ABEL Design Environment without save"
*Edit Menu
1 6 12 24
$BOX
1 1 1 " Delete Line ^D" "Delete the current line"
2 1 1 " Replicate Line ^R" "Replicate the current line"
$LINE
4 1 1 " Search... " "Search for text in file"
5 1 1 " Next ^N" "Next occurrence of search text"
$LINE
7 1 1 " Edit " "Invoke your text editor"
8 1 1 " My Text Editor Is... " "Specify your text editor"
$LINE
10 1 3 " Repaint <<^L>>" "Repaint the entire screen"
*Menu Length
30 12 48
*View Menu
1 12 18 24
$BOX
1 1 10 " Compiler Listing " "View the ABEL-HDL listing file (*.lst)"
2 1 1 " Compiled Equations " "View the compiled equations (from *.tt1)"
3 1 1 " Optimized Equations " "View the optimized equations (from *.tt2)"
4 1 1 " Fitted Equations " "View the fitted equations (from *.tt3)"
$LINE
6 1 1 " Device Candidates " "View the Selector device candidate list (*.sel)"
7 1 8 " Fitter Assignments " "View the pin assignments made by the Fitter (*.fit)"
$LINE
9 1 8 " PLDmap Report " "View the PLDmap documentation file (*.doc)"
10 1 1 " JEDEC/PROM Fuse File " "View the fuse file (*.jed, etc.)"
$LINE
12 1 1 " Simulation Results " "View the latest simulation results (from *.sm?)"
13 1 4 " PLDgrade Report " "View the PLDgrade fault grading results"
$LINE
15 1 1 " Errors " "View errors from the last executed program"
16 1 1 " View File... " "View any file of your choice"
*Compile Menu
1 18 10 24
$BOX
1 1 1 " Compile " "Compile the design and generate .tt1 PLA file"
2 1 1 " Error Check " "Check for syntax errors only"
3 1 1 " Vectors Only " "Compile the test vectors only"
4 1 1 " Options... " "Set the compile processing options"
$LINE
6 1 1 " Simulate Equations " "Simulate the compiled equations"
7 1 1 " Re-Simulate " "Simulate the design with updated test vectors"
8 1 1 " Trace Options... " "Set the equation simulation trace options "
*Optimize Menu
1 27 7 25
$BOX
1 1 1 " Reduce " "Optimize the design with logic reduction"
2 1 1 " Options... " "Set the reduction options"
$LINE
4 1 1 " Simulate Optimized " "Simulate the optimized equations"
5 1 1 " Trace Options... " "Set the optimized simulation trace options"
*SmartPart Menu
1 37 12 26
$BOX
1 1 1 " Database Search " "Search the SmartPart database and select parts"
2 1 1 " Query Database " "Query the SmartPart database (without design)"
3 1 1 " Modify Criteria... " "Set the device selection criteria"
$LINE
5 1 1 " Fit " "Fit the design into specific device(s)"
6 1 10 " Fit from List File " "Fit the design using list of candidate devices"
7 1 1 " Options... " "Set the fitter options"
$LINE
9 1 1 " Simulate Fitted Design " "Simulate the design after fitting"
10 1 1 " Trace Options... " "Set the fit simulation trace options"
*PartMap Menu
1 48 14 27
$BOX
1 1 1 " PLDmap " "Map the design using specified device"
2 1 1 " Options... " "Set the PLDmap options"
$LINE
4 1 1 " Simulate JEDEC <<F4>> " "Simulate the JEDEC file"
5 1 1 " Re-Simulate JEDEC " "Re-Simulate the JEDEC file using new vectors"
6 1 1 " Trace Options... " "Set the JEDEC simulation options"
$LINE
8 1 2 " PLDgrade " "Fault grade the JEDEC file using PLDgrade"
9 1 4 " PLDgrade Options... " "Set PLDgrade options"
$LINE
11 1 9 " Program Device <<Alt-F1>> " "Invoke the terminal emulator"
12 1 5 " PLDtest Plus... " "PLDtest Plus Design Environment"
*Xfer Menu
1 56 4 24
$BOX
1 1 1 " Translate " "Translate ABEL to one of several formats"
2 1 11 " Translate Options... " "Set translation output type"
*Defaults Menu
1 64 9 21
$BOX
1 2 1 " Auto Update " "Enable automatic design update"
2 2 1 " Force Fit Update " "Force fit during auto-update"
$LINE
4 2 1 " Spaces to Tabs " "Convert spaces to tabs when saving file"
5 2 1 " Read Only " "File in editor is read only (no edit)"
$LINE
7 2 1 " Program Pause " "Pause after running any program"
*Help Menu
1 -7 15 22
$BOX
1 1 1 " Help For Help... " "Help on how and when to get help"
$LINE
3 1 1 " Index... " "Indexed help topics"
4 1 1 " Keyboard... " "Help for Keys"
5 1 3 " Design Process... " "Help for ABEL Design Process"
6 1 1 " Menus... " "Help for Menus"
7 1 1 " Program Options... " "Help for ABEL Program Options"
8 1 1 " Language... " "Help for the ABEL-HDL Language"
$LINE
10 1 1 " Devices... " "Help for ABEL Devices"
11 1 1 " Errors... " "Help for ABEL error numbers"
$LINE
13 1 1 " About... " "About the ABEL-HDL design environment"
*File Open form
10 5 7 -9 " File Open " "*File Open Options"
2 3 -1 "File Name: " "*File Open Name"
4 20 0 "< Open >" "*OK Button"
4 40 0 "<Cancel> (<<ESC>>)" "*Cancel Button"
*File Merge form
10 5 7 -9 " File Merge " "*File Merge Options"
2 3 -1 "File Name: " "*File Merge Name"
4 20 0 "< Merge >" "*OK Button"
4 40 0 "<Cancel> (<<ESC>>)" "*Cancel Button"
*Save As form
10 5 7 -9 " Save As " "*Save As Options"
2 3 -1 "New File Name: " "*Save As Name"
4 15 0 "< Save >" "*OK Button"
4 40 0 "<Cancel> (<<ESC>>)" "*Cancel Button"
*Print form
10 5 7 -9 " Print " "*Print Options"
2 3 -1 "File to Print: " "*File Print Name"
4 15 0 "< Print >" "*OK Button"
4 40 0 "<Cancel> (<<ESC>>)" "*Cancel Button"
*Search Editor form
12 5 9 -9 " Search " "*Search Options"
2 3 -1 "Text to Search For: " "*Search String"
4 3 2 "[ ] Case Insensitive Search" "*Search Insensitive"
6 15 2 "< Search >" "*OK Button"
6 40 2 "<Cancel> (<<ESC>>)" "*Cancel Button"
*Select Editor form
14 5 7 -9 " Text Editor " "*Text Editor Options"
2 3 -1 "Text Editor Program Name: " "*Editor Name"
4 15 2 "<OK> <<_OK_>>" "*OK Button"
4 40 2 "<Cancel> (<<ESC>>)" "*Cancel Button"
*Your Choice form
10 5 8 -8 " View File " "*View File Options"
2 3 -1 "File Name: " "*View File"
4 20 0 "< View >" "*OK Button"
4 40 0 "<Cancel> (<<ESC>>)" "*Cancel Button"
*Compile Options form
6 17 13 47 " Compile Options " "*Compile Options"
2 3 2 "( ) No Listing" "*Compile Listing"
3 3 2 "( ) Standard Listing" "*Compile Listing"
4 3 2 "( ) Expanded Listing" "*Compile Listing"
6 3 2 "[ ] Retain Redundancy" "*Compile Retain Redundancy"
8 3 -1 "Module Arguments: " "*Compile Args"
10 13 0 "<OK> <<_OK_>>" "*OK Button"
10 27 0 "<Cancel> (<<ESC>>)" "*Cancel Button"
*Optimize Options form
6 16 15 42 " Reduction Options " "*Optimize Options"
2 3 2 "( ) Use Default" "*Reduction Options"
3 3 2 "( ) Reduce by Pin, Auto Polarity" "*Reduction Options"
4 3 2 "( ) Reduce by Pin, Fixed Polarity" "*Reduction Options"
5 3 2 "( ) Reduce as Group, Auto Polarity" "*Reduction Options"
6 3 2 "( ) Reduce as Group, Fixed Polarity" "*Reduction Options"
7 3 2 "( ) D/T Flip-Flop Auto Synthesize" "*Reduction Options"
8 3 2 "( ) No Reduce, Merge Only" "*Reduction Options"
10 3 2 "[ ] Quine McCluskey Reduction" "*Reduce Exact"
12 5 0 "<OK> <<_OK_>>" "*OK Button"
12 20 0 "<Cancel> (<<ESC>>)" "*Cancel Button"
*Simulate Options form
1 16 21 49 " Simulate Trace Options " "*Simulate Trace Options"
2 3 2 "( ) No Trace" "*Trace Format"
3 3 2 "( ) Pins Format" "*Trace Format"
4 3 2 "( ) Wave Format" "*Trace Format"
5 3 2 "( ) Wave Format ASCII" "*Trace Format"
6 3 2 "( ) Table Format" "*Trace Format"
7 3 2 "( ) Macro-Cell Format" "*Trace Format"
9 3 2 "( ) Register Powerup 0" "*Trace Powerup"
10 3 2 "( ) Register Powerup 1" "*Trace Powerup"
2 28 2 "( ) X-Value 0" "*Trace X Value"
3 28 2 "( ) X-Value 1" "*Trace X Value"
5 28 2 "( ) Z-Value 0" "*Trace Z Value"
6 28 2 "( ) Z-Value 1" "*Trace Z Value"
8 28 2 "( ) Brief Trace" "*Trace Output"
9 28 2 "( ) Detailed Trace" "*Trace Output"
10 28 2 "( ) Clock Trace" "*Trace Output"
12 3 2 "[ ] Use .tmv File" "*Trace .tmv
14 3 -1 "Signal: " "*Trace Signal"
15 3 -1 "First Display Vector: " "*Trace First Vector"
16 3 -1 "Last Display Vector: " "*Trace Last Vector"
18 10 0 "<OK> <<_OK_>>" "*OK Button"
18 25 0 "<Cancel> (<<ESC>>)" "*Cancel Button"
*Select Options form
3 3 19 70 " SmartPart Device Selector Criteria " "*SmartPart Device Selector Criteria"
2 3 32 "Manufacturer : " "*SmartPart Manufacturer"
3 3 32 "Device : " "*SmartPart Device"
4 3 32 "Temperature Spec: " "*SmartPart Temperature Spec."
5 3 32 "Technology : " "*SmartPart Technology"
6 3 32 "Package Type : " "*SmartPart Package Type"
8 3 32 "Preload : " "*SmartPart Jamload"
9 3 32 "Erasable : " "*SmartPart Eraseable"
2 34 64 "Pins : " "*SmartPart Pins"
3 34 64 "Speed (ns) : " "*SmartPart Speed"
4 34 64 "Set-Up Time (ns): " "*SmartPart Set-Up Time"
5 34 64 "Hold Time (ns) : " "*SmartPart Hold Time"
6 34 64 "Price : " "*SmartPart Price"
7 34 64 "Utilization : " "*SmartPart Utilization"
8 34 64 "Power (mW) : " "*SmartPart Power"
9 34 64 "User 1 : " "*SmartPart User"
10 34 64 "User 2 : " "*SmartPart User"
11 3 -1 "Report File Name: " "*SmartPart Report File"
12 3 -1 "Report Sort Order: " "*SmartPart Report Sort Order"
14 3 -1 "Database Directory: " "*SmartPart Database Directory"
16 33 0 "<OK> <<_OK_>>" "*OK Button"
16 47 0 "<Cancel> (<<ESC>>)" "*Cancel Button"
*Fit ABEL Options form
5 12 14 60 " Fitter Options " "*Fitter Options"
1 3 -1 "Device: " "*Fitter Device"
3 3 2 "( ) Attempt to Keep Preassignments" "*Fitter Preassign"
4 3 2 "( ) Ignore Preassignments" "*Fitter Preassign"
5 3 2 "( ) Keep Preassignments" "*Fitter Preassign"
7 3 -1 "Device List File: " "*Fitter Device List File"
8 3 2 "[ ] Stop on First Fit" "*Fitter Stop"
10 3 -1 "Alternate Fit Strategy: " "*Fitter Strategy"
12 20 0 "<OK> <<_OK_>>" "*OK Button"
12 35 0 "<Cancel> (<<ESC>>)" "*Cancel Button"
$HLINE 2 1 58
$HLINE 6 1 58
$HLINE 9 1 58
*Fit Options form
2 3 19 74 " Fitter Options " "*Fitter Options"
1 2 19 "Device: " "*Fitter Device"
1 23 -1 "Device List File: " "*Fitter Device List File"
3 2 2 "( ) Attempt Preassignments" "*Fitter Preassign"
4 2 2 "( ) Ignore Preassignments" "*Fitter Preassign"
5 2 2 "( ) Keep Preassignments" "*Fitter Preassign"
3 35 2 "[ ] Stop on First Fit" "*Fitter Stop"
7 2 2 "( ) Optimize Fit for Area" "*Fitter Optimize"
8 2 2 "( ) Optimize Fit for Speed" "*Fitter Optimize"
9 2 2 "( ) No Optimization" "*Fitter Optimize"
10 2 2 "[ ] Extensive Optimization" "*Fitter Quick"
7 35 2 "[ ] Generate Eqn File" "*Fitter Eqn"
8 35 2 "[ ] Allow Combinational Logic Loops" "*Fitter Loops"
12 2 22 "Delay Max: " "*Fitter Delay Max"
12 35 54 "Area Max: " "*Fitter Area Max"
13 2 -1 "Timing Constraints File: " "*Fitter Timing Constraints"
15 2 -1 "Alternate Fit Strategy: " "*Fitter Strategy"
17 30 0 "<OK> <<_OK_>>" "*OK Button"
17 45 0 "<Cancel> (<<ESC>>)" "*Cancel Button"
*Fuseasm Options form
2 9 21 60 " Fuseasm Options " "*PLDmap Options"
1 3 -1 "Device: " "*PLDmap Device"
3 3 2 "( ) No Checksum" "*PLDmap Checksum"
4 3 2 "( ) Full Checksum" "*PLDmap Checksum"
5 3 2 "( ) Dummy Checksum" "*PLDmap Checksum"
7 3 2 "( ) Brief Document" "*PLDmap Document"
8 3 2 "( ) Long Document" "*PLDmap Document"
9 3 2 "[ ] PLCC Chip Diagram" "*PLDmap PLCC"
11 3 2 "[ ] Turbo" "*PLDmap Turbo"
12 3 2 "[ ] Miser" "*PLDmap Miser"
13 3 2 "[ ] Blow Product Terms" "*PLDmap Blow"
14 3 2 "[ ] Lock" "*PLDmap Lock"
3 31 2 "( ) X-Value 0" "*Trace X Value"
4 31 2 "( ) X-Value 1" "*Trace X Value"
6 31 2 "( ) Default Format" "*PLDmap Format"
7 31 2 "( ) Brief JEDEC Format" "*PLDmap Format"
8 31 2 "( ) Hex JEDEC Format" "*PLDmap Format"
9 31 2 "( ) Full JEDEC Format" "*PLDmap Format"
10 31 2 "( ) 82 PROM Format" "*PLDmap Format"
11 31 2 "( ) 83 PROM Format" "*PLDmap Format"
12 31 2 "( ) 87 PROM Format" "*PLDmap Format"
13 31 2 "( ) 88 PROM Format" "*PLDmap Format"
14 31 2 "( ) POF Format" "*PLDmap Format"
16 3 46 "User Electronic Signature: " "*PLDmap Signature"
17 3 -1 "JEDEC Directory: " "*PLDmap Directory"
19 17 0 "<OK> <<_OK_>>" "*OK Button"
19 30 0 "<Cancel> (<<ESC>>)" "*Cancel Button"
*Fault Options form
5 16 11 49 " PLDgrade Options " "*PLDgrade Options"
2 3 2 "( ) Brief Document" "*PLDgrade Document"
3 3 2 "( ) Long Document" "*PLDgrade Document"
5 3 2 "( ) Register Powerup 0" "*Trace Powerup"
6 3 2 "( ) Register Powerup 1" "*Trace Powerup"
2 31 2 "( ) X-Value 0" "*Trace X Value"
3 31 2 "( ) X-Value 1" "*Trace X Value"
5 31 2 "( ) Z-Value 0" "*Trace Z Value"
6 31 2 "( ) Z-Value 1" "*Trace Z Value"
8 16 0 "<OK> <<_OK_>>" "*OK Button"
8 29 0 "<Cancel> (<<ESC>>)" "*Cancel Button"
*Focus Module form
5 25 7 33 " Focus Module " "*Focus Module"
2 3 -1 "Focus Module: " "*Focus Module"
4 3 0 "<OK> <<_OK_>>" "*OK Button"
4 16 0 "<Cancel> (<<ESC>>)" "*Cancel Button"
*Exit form
10 0 6 53 "" "*Exit"
3 16 0 "<Yes>" "*OK Button"
3 24 0 "<No>" "*Cancel Button"
$TEXT 2 2 "You will lose all of your edits/option changes!"
$TEXT 3 2 "Quit anyway?"
*Xlate Options form
5 22 12 38 " Translate Options " "*Translate Options"
2 3 2 "( ) Xilinx PDS" "*Translation Format"
3 3 2 "( ) Actel PDS" "*Translation Format"
4 3 2 "( ) Plusasm" "*Translation Format"
5 3 2 "( ) Signetics Snap" "*Translation Format"
6 3 2 "( ) PDS" "*Translation Format"
7 3 2 "( ) ABEL-PLA" "*Translation Format"
8 3 2 "( ) MIS .eqn" "*Translation Format"
10 6 0 "<OK> <<_OK_>>" "*OK Button"
10 18 0 "<Cancel> (<<ESC>>)" "*Cancel Button"

9
trunk/workspace/01_EasyAbel/ABELOPT.MNU Normal file
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@@ -0,0 +1,9 @@
ESrIn 88
EEdit "ed"
ESchm ""
ERdOn 0
DAUpd 1
DTabs 0
DPaus 0
DAFit 0

8
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echo off
Rem: HITERM will use ABELPROG.CFG from ABEL4DEV directory.
if not (%ABEL4DEV%) == () HITERM %ABEL4DEV%\ABELPROG.CFG
Rem: HITERM will use ABELPROG.CFG from local directory if ABEL4DEV not defined
if (%ABEL4DEV%) == () HITERM ABELPROG.CFG

BIN
trunk/workspace/01_EasyAbel/ABEL_Tutorial.pdf Normal file
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module actlow
TITLE 'Functional example of active low output signals, 22 July 1992
John Gromala, Data I/O Corporation.'
" Generic example file demonstrating how active low signals are treated
" in simulation (PLASIM).
actlow DEVICE 'p22v10';
"inputs
clock pin 1;
in1 pin 2;
in2 pin 3;
"outputs
!out1 pin 23 ISTYPE 'reg,buffer'; "active low signal
out2 pin 22 ISTYPE 'reg,buffer'; "active high signal
!out3 pin 21 ISTYPE 'reg,invert'; "active low signal
out4 pin 20 ISTYPE 'reg,invert'; "active high signal
" Constant assignments
x, c, H, L = .x., .c., 1, 0 ;
" Set Declaration
outputs = [ out1, out2, out3, out4 ];
equations
out1 := in1 & in2 ;
out2 := in1 & in2 ;
out3 := in1 & in2 ;
out4 := in1 & in2 ;
outputs.clk = clock ;
test_vectors
([ clock, in1, in2 ] -> [ out1, out2, out3, out4 ])
"The first vector is for the power up state. The registers all
"power up LOW but the values at the pins are based on whether there
"is an inverter or buffer from the register to the pin. Since out3
"and out4 have inverters they will be HIGH at their pins as
"demonstrated by the test vectors (look at simulator results).
[ 0 , x , x ] -> [ x , x , x , x ];
"The second vector is written for the equations in the equation section.
"These are all active high equations and the test vectors should be written
"to test the logic for these equations. However, when you view the simulator
"results, signals one and three will be HIGH for their values even though
"the vector is written with LOWS. The reason being these are actually
"active low signals and when the logic is not true their values should be HIGH.
[ c , 0 , 0 ] -> [ L , L , L , L ];
" This vector demonstrates the same as the previous vector except for
"now the logic is true and the signals, one and three, have LOWS as
"their values in the simulator results. However, you write the vector
"for active high logic and thus the highs in the actual vector written.
[ c , 1 , 1 ] -> [ H , H , H , H ];
[ c , 0 , 1 ] -> [ L , L , L , L ];
end

6
trunk/workspace/01_EasyAbel/AHDL/ACTLOW.DMC Normal file
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#$ SOURCEFILE ACTLOW.abl
#$ LISTFILE ACTLOW.lst
#$ MODULE actlow
#$ DEVICE 'p22v10' ASSIGNED
#$ PLAFILE actlow.tt1
#$ JEDECFILE actlow

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Page 1
EZ-ABEL 4.30 - Device Utilization Chart Mon Apr 7 14:54:38 19;4
Functional example of active low output signals, 22 July 1992
John Gromala, Data I/O Corporation.
==== P22V10 Programmed Logic ====
out1.D = ( !in1
# !in2 ); " ISTYPE 'BUFFER'
out1.C = ( clock );
out2.D = ( in1 & in2 ); " ISTYPE 'BUFFER'
out2.C = ( clock );
out3.D = ( in1 & in2 ); " ISTYPE 'INVERT'
out3.C = ( clock );
out4.D = ( !in1
# !in2 ); " ISTYPE 'INVERT'
out4.C = ( clock );
Page 2
EZ-ABEL 4.30 - Device Utilization Chart Mon Apr 7 14:54:38 19;4
Functional example of active low output signals, 22 July 1992
John Gromala, Data I/O Corporation.
==== P22V10 Chip Diagram ====
P22V10
+---------\ /---------+
| \ / |
| ----- |
clock | 1 24 | Vcc
| |
in1 | 2 23 | out1
| |
in2 | 3 22 | out2
| |
| 4 21 | !out3
| |
| 5 20 | !out4
| |
| 6 19 |
| |
| 7 18 |
| |
| 8 17 |
| |
| 9 16 |
| |
| 10 15 |
| |
| 11 14 |
| |
GND | 12 13 |
| |
| |
`---------------------------'
SIGNATURE: N/A
Page 3
EZ-ABEL 4.30 - Device Utilization Chart Mon Apr 7 14:54:38 19;4
Functional example of active low output signals, 22 July 1992
John Gromala, Data I/O Corporation.
==== P22V10 Resource Allocations ====
Device | Resource | Design | Part |
Resources | Available | Requirement | Utilization | Unused
======================|===========|=============|=============|==============
| | | |
Dedicated input pins | 12 | 3 | 3 | 9 ( 75 %)
Combinatorial inputs | 12 | 3 | 3 | 9 ( 75 %)
Registered inputs | - | 0 | - | -
| | | |
Dedicated output pins | - | 4 | - | -
Bidirectional pins | 10 | 0 | 4 | 6 ( 60 %)
Combinatorial outputs | - | 0 | - | -
Registered outputs | - | 4 | - | -
Reg/Com outputs | 10 | - | 4 | 6 ( 60 %)
Two-input XOR | - | 0 | - | -
| | | |
Buried nodes | - | 0 | - | -
Buried registers | - | 0 | - | -
Buried combinatorials | - | 0 | - | -
Page 4
EZ-ABEL 4.30 - Device Utilization Chart Mon Apr 7 14:54:38 19;4
Functional example of active low output signals, 22 July 1992
John Gromala, Data I/O Corporation.
==== P22V10 Product Terms Distribution ====
Signal | Pin | Terms | Terms | Terms
Name | Assigned | Used | Max | Unused
===============================|==========|=======|=======|=======
out1.REG | 23 | 2 | 8 | 6
out2.REG | 22 | 1 | 10 | 9
out3.REG | 21 | 1 | 12 | 11
out4.REG | 20 | 2 | 14 | 12
==== List of Inputs/Feedbacks ====
Signal Name | Pin | Pin Type
============================== |==========|=========
clock | 1 | CLK/IN
in1 | 2 | INPUT
in2 | 3 | INPUT
Page 5
EZ-ABEL 4.30 - Device Utilization Chart Mon Apr 7 14:54:38 19;4
Functional example of active low output signals, 22 July 1992
John Gromala, Data I/O Corporation.
==== P22V10 Unused Resources ====
Pin | Pin | Product | Flip-flop
Number | Type | Terms | Type
=======|========|=============|==========
4 | INPUT | - | -
5 | INPUT | - | -
6 | INPUT | - | -
7 | INPUT | - | -
8 | INPUT | - | -
9 | INPUT | - | -
10 | INPUT | - | -
11 | INPUT | - | -
13 | INPUT | - | -
14 | BIDIR | NORMAL 8 | D
15 | BIDIR | NORMAL 10 | D
16 | BIDIR | NORMAL 12 | D
17 | BIDIR | NORMAL 14 | D
18 | BIDIR | NORMAL 16 | D
19 | BIDIR | NORMAL 16 | D
Page 6
EZ-ABEL 4.30 - Device Utilization Chart Mon Apr 7 14:54:38 19;4
Functional example of active low output signals, 22 July 1992
John Gromala, Data I/O Corporation.
==== I/O Files ====
Module: 'actlow'
Input files
===========
ABEL PLA file: actlow.tt2
Vector file: actlow.tmv
Device library: P22V10.dev
Output files
============
Report file: actlow.doc
Programmer load file: actlow.jed

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EZ-ABEL 4.32 Data I/O Corp. JEDEC file for: P22V10 V9.0
Created on: Mon Apr 7 14:54:38 19;4
Functional example of active low output signals, 22 July 1992
John Gromala, Data I/O Corporation.
*
QP24* QF5828* QV4* F0*
X0*
NOTE Table of pin names and numbers*
NOTE PINS clock:1 in1:2 in2:3 out1:23 out2:22 out3:21 out4:20*
L0044 11111111111111111111111111111111111111111111*
L0088 11111011111111111111111111111111111111111111*
L0132 11111111101111111111111111111111111111111111*
L0440 11111111111111111111111111111111111111111111*
L0484 11110111011111111111111111111111111111111111*
L0924 11111111111111111111111111111111111111111111*
L0968 11110111011111111111111111111111111111111111*
L1496 11111111111111111111111111111111111111111111*
L1540 11111011111111111111111111111111111111111111*
L1584 11111111101111111111111111111111111111111111*
L5808 10100000000000000000*
V0001 0XXXXXXXXXXNXXXXXXXNNNNN*
V0002 C00XXXXXXXXNXXXXXXXLHLHN*
V0003 C11XXXXXXXXNXXXXXXXHLHLN*
V0004 C01XXXXXXXXNXXXXXXXLHLHN*
C3668*
EDA7

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0001 |module actlow
0002 |
0003 |TITLE 'Functional example of active low output signals, 22 July 1992
0004 | John Gromala, Data I/O Corporation.'
0005 |
0006 |" Generic example file demonstrating how active low signals are treated
0007 |" in simulation (PLASIM).
0008 |
0009 |actlow DEVICE 'p22v10';
0010 |
0011 |"inputs
0012 |
0013 | clock pin 1;
0014 | in1 pin 2;
0015 | in2 pin 3;
0016 |
0017 |"outputs
0018 |
0019 | !out1 pin 23 ISTYPE 'reg,buffer'; "active low signal
0020 | out2 pin 22 ISTYPE 'reg,buffer'; "active high signal
0021 |
0022 | !out3 pin 21 ISTYPE 'reg,invert'; "active low signal
0023 | out4 pin 20 ISTYPE 'reg,invert'; "active high signal
0024 |
0025 |" Constant assignments
0026 |
0027 | x, c, H, L = .x., .c., 1, 0 ;
0028 |
0029 |" Set Declaration
0030 |
0031 | outputs = [ out1, out2, out3, out4 ];
0032 |
0033 |equations
0034 |
0035 | out1 := in1 & in2 ;
0036 | out2 := in1 & in2 ;
0037 |
0038 | out3 := in1 & in2 ;
0039 | out4 := in1 & in2 ;
0040 |
0041 | outputs.clk = clock ;
0042 |
0043 |test_vectors
0044 |
0045 | ([ clock, in1, in2 ] -> [ out1, out2, out3, out4 ])
0046 |
0047 |"The first vector is for the power up state. The registers all
0048 |"power up LOW but the values at the pins are based on whether there
0049 |"is an inverter or buffer from the register to the pin. Since out3
0050 |"and out4 have inverters they will be HIGH at their pins as
0051 |"demonstrated by the test vectors (look at simulator results).
0052 |
0053 | [ 0 , x , x ] -> [ x , x , x , x ];
0054 |
0055 |"The second vector is written for the equations in the equation section.
0056 |"These are all active high equations and the test vectors should be written
0057 |"to test the logic for these equations. However, when you view the simulator
0058 |"results, signals one and three will be HIGH for their values even though
0059 |"the vector is written with LOWS. The reason being these are actually
0060 |"active low signals and when the logic is not true their values should be HIGH.
0061 |
0062 | [ c , 0 , 0 ] -> [ L , L , L , L ];
0063 |
0064 |" This vector demonstrates the same as the previous vector except for
0065 |"now the logic is true and the signals, one and three, have LOWS as
0066 |"their values in the simulator results. However, you write the vector
0067 |"for active high logic and thus the highs in the actual vector written.
0068 |
0069 | [ c , 1 , 1 ] -> [ H , H , H , H ];
0070 | [ c , 0 , 1 ] -> [ L , L , L , L ];
0071 |
0072 |end
0073 |
0074 |
0075 |
0076 |
0077 |
0078 |
0079 |
0080 |
0081 |
0082 |
0083 |
0084 |
0085 |
0086 |
0087 |
0088 |
0089 |
0090 |
0091 |
0092 |
0093 |
0094 |
0095 |
0096 |
0097 |
0098 |
0099 |
0100 |
0101 |
0102 |
0103 |
0104 |
0105 |
0106 |
0107 |
0108 |
0109 |
0110 |
0111 |
0112 |

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Simulate EZ-ABEL 4.30 Date: Mon Apr 7 14:54:38 19;4
Fuse file: 'actlow.jed' Vector file: 'actlow.jed' Part: 'P22V10'
EZ-ABEL 4.32 Data I/O Corp. JEDEC file for: P22V10 V9.0
Created on: Mon Apr 7 14:54:38 19;4
Functional example of active low output signals, 22 July 1992
John Gromala, Data I/O Corporation.
c
l o o o o
o i i u u u u
c n n t t t t
k 1 2 4 3 2 1
V0001 0 0 0 H H L L
V0002 C 0 0 L H L H
V0003 C 1 1 H L H L
V0004 C 0 1 L H L H
4 out of 4 vectors passed.

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#$ TOOL EZ-ABEL 4.30
#$ MODULE actlow
#$ TITLE Functional example of active low output signals, 22 July 1992
#$ TITLE John Gromala, Data I/O Corporation.
S7;
clock in1 in2 -> out1 out2 out3 out4
$
0XX->XXXX;
C00->1010;
C11->0101;
C01->1010;
$

BIN
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Binary file not shown.

BIN
trunk/workspace/01_EasyAbel/AHDL/ACTLOW.TT2 Normal file
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Binary file not shown.

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module BARREL
title '8-bit barrel shifter
Don Flaherty Data I/O Corp 12 Oct 1992'
barrel device 'P20R8';
D7,D6,D5,D4,D3,D2,D1,D0 Pin 2,3,4,5,6,7,8,9;
Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0 Pin 15,16,17,18,19,20,21,22;
Clk,OC,E,I2,I1,I0 Pin 1,13,23,10,11,14;
Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0 istype 'reg,invert';
Input = [D7,D6,D5,D4,D3,D2,D1,D0];
Output = [Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0];
Sel = [I2,I1,I0];
H,L,C,Z = 1,0,.C.,.Z.;
equations
Output.clk = Clk;
Output.oe = !OC;
!Output := E & ( (Sel == 0) & ![D7,D6,D5,D4,D3,D2,D1,D0]
# (Sel == 1) & ![D0,D7,D6,D5,D4,D3,D2,D1]
# (Sel == 2) & ![D1,D0,D7,D6,D5,D4,D3,D2]
# (Sel == 3) & ![D2,D1,D0,D7,D6,D5,D4,D3]
# (Sel == 4) & ![D3,D2,D1,D0,D7,D6,D5,D4]
# (Sel == 5) & ![D4,D3,D2,D1,D0,D7,D6,D5]
# (Sel == 6) & ![D5,D4,D3,D2,D1,D0,D7,D6]
# (Sel == 7) & ![D6,D5,D4,D3,D2,D1,D0,D7]) ;
test_vectors
([Clk,OC, E, Sel, Input] -> Output)
[ C, L, H, 0, ^b10000000] -> ^b10000000; " Shift 0
[ C, L, H, 1, ^b10000000] -> ^b01000000; " Shift 1
[ C, L, H, 2, ^b10000000] -> ^b00100000; " Shift 2
[ C, L, H, 3, ^b10000000] -> ^b00010000; " Shift 3
[ C, L, H, 4, ^b10000000] -> ^b00001000; " Shift 4
[ C, L, H, 5, ^b10000000] -> ^b00000100; " Shift 5
[ C, L, H, 6, ^b10000000] -> ^b00000010; " Shift 6
[ C, L, H, 7, ^b10000000] -> ^b00000001; " Shift 7
[ C, L, H, 0, ^b01111111] -> ^b01111111; " Shift 0
[ C, L, H, 1, ^b01111111] -> ^b10111111; " Shift 1
[ C, L, H, 3, ^b01111111] -> ^b11101111; " Shift 3
[ C, L, H, 7, ^b01111111] -> ^b11111110; " Shift 7
[ C, L, H, 1, ^b00000001] -> ^b10000000; " Shift 1/Wrap
[ C, L, H, 1, ^b11111110] -> ^b01111111; " Shift 1/Wrap
[ C, L, L, 0, ^b00000000] -> ^b11111111; " Preset
[ C, H, H, 0, ^b00000000] -> Z; " Test High Z
end

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#$ SOURCEFILE BARREL.abl
#$ LISTFILE BARREL.lst
#$ MODULE barrel
#$ DEVICE 'P20R8' ASSIGNED
#$ PLAFILE barrel.tt1
#$ JEDECFILE barrel

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Page 1
EZ-ABEL 4.30 - Device Utilization Chart Mon Apr 7 14:53:25 19;4
8-bit barrel shifter
Don Flaherty Data I/O Corp 12 Oct 1992
==== P20R8 Programmed Logic ====
Q7.D = ( !D6 & E & I2 & I1 & I0
# !D2 & E & !I2 & I1 & I0
# !D4 & E & I2 & !I1 & I0
# !D0 & E & !I2 & !I1 & I0
# !D5 & E & I2 & I1 & !I0
# !D1 & E & !I2 & I1 & !I0
# !D3 & E & I2 & !I1 & !I0
# !D7 & E & !I2 & !I1 & !I0 ); " ISTYPE 'INVERT'
Q7.C = ( Clk );
Q7.OE = ( !OC );
Q6.D = ( !D5 & E & I2 & I1 & I0
# !D1 & E & !I2 & I1 & I0
# !D3 & E & I2 & !I1 & I0
# !D7 & E & !I2 & !I1 & I0
# !D4 & E & I2 & I1 & !I0
# !D0 & E & !I2 & I1 & !I0
# !D2 & E & I2 & !I1 & !I0
# !D6 & E & !I2 & !I1 & !I0 ); " ISTYPE 'INVERT'
Q6.C = ( Clk );
Q6.OE = ( !OC );
Q5.D = ( !D4 & E & I2 & I1 & I0
# !D0 & E & !I2 & I1 & I0
# !D2 & E & I2 & !I1 & I0
# !D6 & E & !I2 & !I1 & I0
# !D3 & E & I2 & I1 & !I0
# !D7 & E & !I2 & I1 & !I0
# !D1 & E & I2 & !I1 & !I0
# !D5 & E & !I2 & !I1 & !I0 ); " ISTYPE 'INVERT'
Q5.C = ( Clk );
Q5.OE = ( !OC );
Q4.D = ( !D3 & E & I2 & I1 & I0
# !D7 & E & !I2 & I1 & I0
# !D1 & E & I2 & !I1 & I0
# !D5 & E & !I2 & !I1 & I0
# !D2 & E & I2 & I1 & !I0
# !D6 & E & !I2 & I1 & !I0
# !D0 & E & I2 & !I1 & !I0
# !D4 & E & !I2 & !I1 & !I0 ); " ISTYPE 'INVERT'
Q4.C = ( Clk );
Q4.OE = ( !OC );
Q3.D = ( !D2 & E & I2 & I1 & I0
# !D6 & E & !I2 & I1 & I0
# !D0 & E & I2 & !I1 & I0
# !D4 & E & !I2 & !I1 & I0
# !D1 & E & I2 & I1 & !I0
Page 2
EZ-ABEL 4.30 - Device Utilization Chart Mon Apr 7 14:53:26 19;4
8-bit barrel shifter
Don Flaherty Data I/O Corp 12 Oct 1992
==== P20R8 Programmed Logic ====
# !D5 & E & !I2 & I1 & !I0
# !D7 & E & I2 & !I1 & !I0
# !D3 & E & !I2 & !I1 & !I0 ); " ISTYPE 'INVERT'
Q3.C = ( Clk );
Q3.OE = ( !OC );
Q2.D = ( !D1 & E & I2 & I1 & I0
# !D5 & E & !I2 & I1 & I0
# !D7 & E & I2 & !I1 & I0
# !D3 & E & !I2 & !I1 & I0
# !D0 & E & I2 & I1 & !I0
# !D4 & E & !I2 & I1 & !I0
# !D6 & E & I2 & !I1 & !I0
# !D2 & E & !I2 & !I1 & !I0 ); " ISTYPE 'INVERT'
Q2.C = ( Clk );
Q2.OE = ( !OC );
Q1.D = ( !D0 & E & I2 & I1 & I0
# !D4 & E & !I2 & I1 & I0
# !D6 & E & I2 & !I1 & I0
# !D2 & E & !I2 & !I1 & I0
# !D7 & E & I2 & I1 & !I0
# !D3 & E & !I2 & I1 & !I0
# !D5 & E & I2 & !I1 & !I0
# !D1 & E & !I2 & !I1 & !I0 ); " ISTYPE 'INVERT'
Q1.C = ( Clk );
Q1.OE = ( !OC );
Q0.D = ( !D7 & E & I2 & I1 & I0
# !D3 & E & !I2 & I1 & I0
# !D5 & E & I2 & !I1 & I0
# !D1 & E & !I2 & !I1 & I0
# !D6 & E & I2 & I1 & !I0
# !D2 & E & !I2 & I1 & !I0
# !D4 & E & I2 & !I1 & !I0
# !D0 & E & !I2 & !I1 & !I0 ); " ISTYPE 'INVERT'
Q0.C = ( Clk );
Q0.OE = ( !OC );
Page 3
EZ-ABEL 4.30 - Device Utilization Chart Mon Apr 7 14:53:26 19;4
8-bit barrel shifter
Don Flaherty Data I/O Corp 12 Oct 1992
==== P20R8 Chip Diagram ====
P20R8
+---------\ /---------+
| \ / |
| ----- |
Clk | 1 24 | Vcc
| |
D7 | 2 23 | E
| |
D6 | 3 22 | !Q0
| |
D5 | 4 21 | !Q1
| |
D4 | 5 20 | !Q2
| |
D3 | 6 19 | !Q3
| |
D2 | 7 18 | !Q4
| |
D1 | 8 17 | !Q5
| |
D0 | 9 16 | !Q6
| |
I2 | 10 15 | !Q7
| |
I1 | 11 14 | I0
| |
GND | 12 13 | OC
| |
| |
`---------------------------'
SIGNATURE: N/A
Page 4
EZ-ABEL 4.30 - Device Utilization Chart Mon Apr 7 14:53:26 19;4
8-bit barrel shifter
Don Flaherty Data I/O Corp 12 Oct 1992
==== P20R8 Resource Allocations ====
Device | Resource | Design | Part |
Resources | Available | Requirement | Utilization | Unused
======================|===========|=============|=============|==============
| | | |
Dedicated input pins | 12 | 14 | 12 | 0 ( 0 %)
Combinatorial inputs | 12 | 12 | 12 | 0 ( 0 %)
Registered inputs | - | 0 | - | -
| | | |
Dedicated output pins | 8 | 8 | 8 | 0 ( 0 %)
Bidirectional pins | - | 0 | - | -
Combinatorial outputs | - | 0 | - | -
Registered outputs | 8 | 8 | 8 | 0 ( 0 %)
Two-input XOR | - | 0 | - | -
| | | |
Buried nodes | - | 0 | - | -
Buried registers | - | 0 | - | -
Buried combinatorials | - | 0 | - | -
Page 5
EZ-ABEL 4.30 - Device Utilization Chart Mon Apr 7 14:53:26 19;4
8-bit barrel shifter
Don Flaherty Data I/O Corp 12 Oct 1992
==== P20R8 Product Terms Distribution ====
Signal | Pin | Terms | Terms | Terms
Name | Assigned | Used | Max | Unused
===============================|==========|=======|=======|=======
Q7.REG | 15 | 8 | 8 | 0
Q6.REG | 16 | 8 | 8 | 0
Q5.REG | 17 | 8 | 8 | 0
Q4.REG | 18 | 8 | 8 | 0
Q3.REG | 19 | 8 | 8 | 0
Q2.REG | 20 | 8 | 8 | 0
Q1.REG | 21 | 8 | 8 | 0
Q0.REG | 22 | 8 | 8 | 0
==== List of Inputs/Feedbacks ====
Signal Name | Pin | Pin Type
============================== |==========|=========
D7 | 2 | INPUT
D6 | 3 | INPUT
D5 | 4 | INPUT
D4 | 5 | INPUT
D3 | 6 | INPUT
D2 | 7 | INPUT
D1 | 8 | INPUT
D0 | 9 | INPUT
Clk | 1 | CLK
OC | 13 | OE
E | 23 | INPUT
I2 | 10 | INPUT
I1 | 11 | INPUT
I0 | 14 | INPUT
Page 6
EZ-ABEL 4.30 - Device Utilization Chart Mon Apr 7 14:53:26 19;4
8-bit barrel shifter
Don Flaherty Data I/O Corp 12 Oct 1992
==== P20R8 Unused Resources ====
Pin | Pin | Product | Flip-flop
Number | Type | Terms | Type
=======|========|=============|==========
- | - | - | -
Page 7
EZ-ABEL 4.30 - Device Utilization Chart Mon Apr 7 14:53:26 19;4
8-bit barrel shifter
Don Flaherty Data I/O Corp 12 Oct 1992
==== I/O Files ====
Module: 'barrel'
Input files
===========
ABEL PLA file: barrel.tt2
Vector file: barrel.tmv
Device library: P20R8.dev
Output files
============
Report file: barrel.doc
Programmer load file: barrel.jed

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EZ-ABEL 4.32 Data I/O Corp. JEDEC file for: P20R8 V9.0
Created on: Mon Apr 7 14:53:26 19;4
8-bit barrel shifter
Don Flaherty Data I/O Corp 12 Oct 1992
*
QP24* QF2560* QV16* F0*
X0*
NOTE Table of pin names and numbers*
NOTE PINS D7:2 D6:3 D5:4 D4:5 D3:6 D2:7 D1:8 D0:9 Q7:15 Q6:16 Q5:17*
NOTE PINS Q4:18 Q3:19 Q2:20 Q1:21 Q0:22 Clk:1 OC:13 E:23 I2:10 I1:11 I0:14*
L0000 1001111111111111111111111111111101110101*
L0040 1101111111111111101111111111111110110101*
L0080 1101111110111111111111111111111101111001*
L0120 1101111111111111111111111011111110111001*
L0160 1101101111111111111111111111111101110110*
L0200 1101111111111111111110111111111110110110*
L0240 1101111111111011111111111111111101111010*
L0280 1101111111111111111111111111101110111010*
L0320 1101111111111111111111111111101101110101*
L0360 1101111111111011111111111111111110110101*
L0400 1101101111111111111111111111111101111001*
L0440 1101111111111111111110111111111110111001*
L0480 1001111111111111111111111111111101110110*
L0520 1101111111111111101111111111111110110110*
L0560 1101111110111111111111111111111101111010*
L0600 1101111111111111111111111011111110111010*
L0640 1101111111111111111111111011111101110101*
L0680 1101111110111111111111111111111110110101*
L0720 1001111111111111111111111111111101111001*
L0760 1101111111111111101111111111111110111001*
L0800 1101111111111111111111111111101101110110*
L0840 1101111111111011111111111111111110110110*
L0880 1101101111111111111111111111111101111010*
L0920 1101111111111111111110111111111110111010*
L0960 1101111111111111111110111111111101110101*
L1000 1101101111111111111111111111111110110101*
L1040 1101111111111111111111111111101101111001*
L1080 1101111111111011111111111111111110111001*
L1120 1101111111111111111111111011111101110110*
L1160 1101111110111111111111111111111110110110*
L1200 1001111111111111111111111111111101111010*
L1240 1101111111111111101111111111111110111010*
L1280 1101111111111111101111111111111101110101*
L1320 1001111111111111111111111111111110110101*
L1360 1101111111111111111111111011111101111001*
L1400 1101111110111111111111111111111110111001*
L1440 1101111111111111111110111111111101110110*
L1480 1101101111111111111111111111111110110110*
L1520 1101111111111111111111111111101101111010*
L1560 1101111111111011111111111111111110111010*
L1600 1101111111111011111111111111111101110101*
L1640 1101111111111111111111111111101110110101*
L1680 1101111111111111111110111111111101111001*
L1720 1101101111111111111111111111111110111001*
L1760 1101111111111111101111111111111101110110*
L1800 1001111111111111111111111111111110110110*
L1840 1101111111111111111111111011111101111010*
L1880 1101111110111111111111111111111110111010*
L1920 1101111110111111111111111111111101110101*
L1960 1101111111111111111111111011111110110101*
L2000 1101111111111111101111111111111101111001*
L2040 1001111111111111111111111111111110111001*
L2080 1101111111111011111111111111111101110110*
L2120 1101111111111111111111111111101110110110*
L2160 1101111111111111111110111111111101111010*
L2200 1101101111111111111111111111111110111010*
L2240 1101101111111111111111111111111101110101*
L2280 1101111111111111111110111111111110110101*
L2320 1101111111111011111111111111111101111001*
L2360 1101111111111111111111111111101110111001*
L2400 1101111110111111111111111111111101110110*
L2440 1101111111111111111111111011111110110110*
L2480 1101111111111111101111111111111101111010*
L2520 1001111111111111111111111111111110111010*
V0001 C1000000000N00HLLLLLLL1N*
V0002 C1000000000N01LHLLLLLL1N*
V0003 C1000000001N00LLHLLLLL1N*
V0004 C1000000001N01LLLHLLLL1N*
V0005 C1000000010N00LLLLHLLL1N*
V0006 C1000000010N01LLLLLHLL1N*
V0007 C1000000011N00LLLLLLHL1N*
V0008 C1000000011N01LLLLLLLH1N*
V0009 C0111111100N00LHHHHHHH1N*
V0010 C0111111100N01HLHHHHHH1N*
V0011 C0111111101N01HHHLHHHH1N*
V0012 C0111111111N01HHHHHHHL1N*
V0013 C0000000100N01HLLLLLLL1N*
V0014 C1111111000N01LHHHHHHH1N*
V0015 C0000000000N00HHHHHHHH0N*
V0016 C0000000000N10ZZZZZZZZ1N*
C1B20*
1892

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0001 |module BARREL
0002 |title '8-bit barrel shifter
0003 |Don Flaherty Data I/O Corp 12 Oct 1992'
0004 |
0005 | barrel device 'P20R8';
0006 |
0007 | D7,D6,D5,D4,D3,D2,D1,D0 Pin 2,3,4,5,6,7,8,9;
0008 | Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0 Pin 15,16,17,18,19,20,21,22;
0009 | Clk,OC,E,I2,I1,I0 Pin 1,13,23,10,11,14;
0010 |
0011 | Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0 istype 'reg,invert';
0012 |
0013 | Input = [D7,D6,D5,D4,D3,D2,D1,D0];
0014 | Output = [Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0];
0015 | Sel = [I2,I1,I0];
0016 | H,L,C,Z = 1,0,.C.,.Z.;
0017 |
0018 |equations
0019 | Output.clk = Clk;
0020 | Output.oe = !OC;
0021 |
0022 | !Output := E & ( (Sel == 0) & ![D7,D6,D5,D4,D3,D2,D1,D0]
0023 | # (Sel == 1) & ![D0,D7,D6,D5,D4,D3,D2,D1]
0024 | # (Sel == 2) & ![D1,D0,D7,D6,D5,D4,D3,D2]
0025 | # (Sel == 3) & ![D2,D1,D0,D7,D6,D5,D4,D3]
0026 | # (Sel == 4) & ![D3,D2,D1,D0,D7,D6,D5,D4]
0027 | # (Sel == 5) & ![D4,D3,D2,D1,D0,D7,D6,D5]
0028 | # (Sel == 6) & ![D5,D4,D3,D2,D1,D0,D7,D6]
0029 | # (Sel == 7) & ![D6,D5,D4,D3,D2,D1,D0,D7]) ;
0030 |
0031 |test_vectors
0032 | ([Clk,OC, E, Sel, Input] -> Output)
0033 | [ C, L, H, 0, ^b10000000] -> ^b10000000; " Shift 0
0034 | [ C, L, H, 1, ^b10000000] -> ^b01000000; " Shift 1
0035 | [ C, L, H, 2, ^b10000000] -> ^b00100000; " Shift 2
0036 | [ C, L, H, 3, ^b10000000] -> ^b00010000; " Shift 3
0037 | [ C, L, H, 4, ^b10000000] -> ^b00001000; " Shift 4
0038 | [ C, L, H, 5, ^b10000000] -> ^b00000100; " Shift 5
0039 | [ C, L, H, 6, ^b10000000] -> ^b00000010; " Shift 6
0040 | [ C, L, H, 7, ^b10000000] -> ^b00000001; " Shift 7
0041 |
0042 | [ C, L, H, 0, ^b01111111] -> ^b01111111; " Shift 0
0043 | [ C, L, H, 1, ^b01111111] -> ^b10111111; " Shift 1
0044 | [ C, L, H, 3, ^b01111111] -> ^b11101111; " Shift 3
0045 | [ C, L, H, 7, ^b01111111] -> ^b11111110; " Shift 7
0046 |
0047 | [ C, L, H, 1, ^b00000001] -> ^b10000000; " Shift 1/Wrap
0048 | [ C, L, H, 1, ^b11111110] -> ^b01111111; " Shift 1/Wrap
0049 | [ C, L, L, 0, ^b00000000] -> ^b11111111; " Preset
0050 | [ C, H, H, 0, ^b00000000] -> Z; " Test High Z
0051 |end

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Simulate EZ-ABEL 4.30 Date: Mon Apr 7 14:53:26 19;4
Fuse file: 'barrel.jed' Vector file: 'barrel.jed' Part: 'P20R8'
EZ-ABEL 4.32 Data I/O Corp. JEDEC file for: P20R8 V9.0
Created on: Mon Apr 7 14:53:26 19;4
8-bit barrel shifter
Don Flaherty Data I/O Corp 12 Oct 1992
C
l D D D D D D D D I I O I Q Q Q Q Q Q Q Q
k 7 6 5 4 3 2 1 0 2 1 C 0 7 6 5 4 3 2 1 0 E
V0001 C 1 0 0 0 0 0 0 0 0 0 0 0 H L L L L L L L 1
V0002 C 1 0 0 0 0 0 0 0 0 0 0 1 L H L L L L L L 1
V0003 C 1 0 0 0 0 0 0 0 0 1 0 0 L L H L L L L L 1
V0004 C 1 0 0 0 0 0 0 0 0 1 0 1 L L L H L L L L 1
V0005 C 1 0 0 0 0 0 0 0 1 0 0 0 L L L L H L L L 1
V0006 C 1 0 0 0 0 0 0 0 1 0 0 1 L L L L L H L L 1
V0007 C 1 0 0 0 0 0 0 0 1 1 0 0 L L L L L L H L 1
V0008 C 1 0 0 0 0 0 0 0 1 1 0 1 L L L L L L L H 1
V0009 C 0 1 1 1 1 1 1 1 0 0 0 0 L H H H H H H H 1
V0010 C 0 1 1 1 1 1 1 1 0 0 0 1 H L H H H H H H 1
V0011 C 0 1 1 1 1 1 1 1 0 1 0 1 H H H L H H H H 1
V0012 C 0 1 1 1 1 1 1 1 1 1 0 1 H H H H H H H L 1
V0013 C 0 0 0 0 0 0 0 1 0 0 0 1 H L L L L L L L 1
V0014 C 1 1 1 1 1 1 1 0 0 0 0 1 L H H H H H H H 1
V0015 C 0 0 0 0 0 0 0 0 0 0 0 0 H H H H H H H H 0
V0016 C 0 0 0 0 0 0 0 0 0 0 1 0 Z Z Z Z Z Z Z Z 1
16 out of 16 vectors passed.

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#$ TOOL EZ-ABEL 4.30
#$ MODULE BARREL
#$ TITLE 8-bit barrel shifter
#$ TITLE Don Flaherty Data I/O Corp 12 Oct 1992
S22;
Clk OC E I2 I1 I0 D7 D6 D5 D4 D3 D2 D1 D0 -> Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
$
C0100010000000->10000000;
C0100110000000->01000000;
C0101010000000->00100000;
C0101110000000->00010000;
C0110010000000->00001000;
C0110110000000->00000100;
C0111010000000->00000010;
C0111110000000->00000001;
C0100001111111->01111111;
C0100101111111->10111111;
C0101101111111->11101111;
C0111101111111->11111110;
C0100100000001->10000000;
C0100111111110->01111111;
C0000000000000->11111111;
C1100000000000->ZZZZZZZZ;
$

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module BCD7
title 'seven segment display decoder 1 Aug 1990
Walter Bright Data I/O Corp Redmond WA'
" a
" --- BCD-to-seven-segment decoder similar to the 7449
" f| g |b
" --- segment identification
" e| d |c
" ---
bcd7 device 'P16P8';
D3,D2,D1,D0 pin 2,3,4,5;
a,b,c,d,e,f,g pin 13,14,15,16,17,18,19 istype 'com';
bcd = [D3,D2,D1,D0];
led = [a,b,c,d,e,f,g];
ON,OFF = 0,1; " for common anode LEDs
L,H,X,Z = 0,1,.X.,.Z.;
@dcset
truth_table (bcd -> [ a , b , c , d , e , f , g ])
0 -> [ ON, ON, ON, ON, ON, ON, OFF]; " 0
1 -> [OFF, ON, ON, OFF, OFF, OFF, OFF]; " 1
2 -> [ ON, ON, OFF, ON, ON, OFF, ON]; " 2
3 -> [ ON, ON, ON, ON, OFF, OFF, ON]; " 3
4 -> [OFF, ON, ON, OFF, OFF, ON, ON]; " 4
5 -> [ ON, OFF, ON, ON, OFF, ON, ON]; " 5
6 -> [ ON, OFF, ON, ON, ON, ON, ON]; " 6
7 -> [ ON, ON, ON, OFF, OFF, OFF, OFF]; " 7
8 -> [ ON, ON, ON, ON, ON, ON, ON]; " 8
9 -> [ ON, ON, ON, ON, OFF, ON, ON]; " 9
10 -> [ ON, ON, ON, OFF, ON, ON, ON]; " A
11 -> [ ON, ON, ON, ON, ON, ON, ON]; " B
12 -> [ ON, OFF, OFF, ON, ON, ON, OFF]; " C
13 -> [OFF, ON, ON, ON, ON, OFF, ON]; " d
14 -> [ ON, OFF, OFF, ON, ON, ON, ON]; " E
15 -> [ ON, OFF, OFF, OFF, ON, ON, ON]; " F
test_vectors (bcd -> [ a , b , c , d , e , f , g ])
0 -> [ ON, ON, ON, ON, ON, ON, OFF];
1 -> [OFF, ON, ON, OFF, OFF, OFF, OFF];
2 -> [ ON, ON, OFF, ON, ON, OFF, ON];
3 -> [ ON, ON, ON, ON, OFF, OFF, ON];
4 -> [OFF, ON, ON, OFF, OFF, ON, ON];
5 -> [ ON, OFF, ON, ON, OFF, ON, ON];
6 -> [ ON, OFF, ON, ON, ON, ON, ON];
7 -> [ ON, ON, ON, OFF, OFF, OFF, OFF];
8 -> [ ON, ON, ON, ON, ON, ON, ON];
9 -> [ ON, ON, ON, ON, OFF, ON, ON];
10 -> [ ON, ON, ON, OFF, ON, ON, ON];
11 -> [ ON, ON, ON, ON, ON, ON, ON];
12 -> [ ON, OFF, OFF, ON, ON, ON, OFF];
13 -> [OFF, ON, ON, ON, ON, OFF, ON];
14 -> [ ON, OFF, OFF, ON, ON, ON, ON];
15 -> [ ON, OFF, OFF, OFF, ON, ON, ON];
end

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#$ SOURCEFILE BCD7.abl
#$ LISTFILE BCD7.lst
#$ MODULE bcd7
#$ DEVICE 'P16P8' ASSIGNED
#$ PLAFILE bcd7.tt1
#$ JEDECFILE bcd7

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Page 1
EZ-ABEL 4.30 - Device Utilization Chart Fri Jun 27 13:01:23 19;4
seven segment display decoder 1 Aug 1990
Walter Bright Data I/O Corp Redmond WA
==== P16P8 Programmed Logic ====
g = ( !D3 & !D2 & !D1
# !D3 & D2 & D1 & D0
# D3 & D2 & !D1 & !D0 );
f = ( !D3 & !D2 & D1
# !D3 & D1 & D0
# !D3 & !D2 & D0
# D3 & D2 & !D1 & D0 );
e = ( !D3 & D2 & !D1
# !D3 & D0
# !D2 & !D1 & D0 );
d = ( D2 & D1 & D0
# !D3 & !D2 & !D1 & D0
# D3 & !D2 & D1 & !D0
# !D3 & D2 & !D1 & !D0 );
c = ( D3 & D2 & !D0
# D3 & D2 & D1
# !D3 & !D2 & D1 & !D0 );
b = !( !D2
# !D3 & D1 & D0
# D3 & !D1 & D0
# !D3 & !D1 & !D0 );
a = ( D3 & D2 & !D1 & D0
# !D3 & !D2 & !D1 & D0
# !D3 & D2 & !D1 & !D0 );
Page 2
EZ-ABEL 4.30 - Device Utilization Chart Fri Jun 27 13:01:23 19;4
seven segment display decoder 1 Aug 1990
Walter Bright Data I/O Corp Redmond WA
==== P16P8 Chip Diagram ====
P16P8
+---------\ /---------+
| \ / |
| ----- |
| 1 20 | Vcc
| |
D3 | 2 19 | !g
| |
D2 | 3 18 | !f
| |
D1 | 4 17 | !e
| |
D0 | 5 16 | !d
| |
| 6 15 | !c
| |
| 7 14 | !b
| |
| 8 13 | !a
| |
| 9 12 |
| |
GND | 10 11 |
| |
| |
`---------------------------'
SIGNATURE: N/A
Page 3
EZ-ABEL 4.30 - Device Utilization Chart Fri Jun 27 13:01:23 19;4
seven segment display decoder 1 Aug 1990
Walter Bright Data I/O Corp Redmond WA
==== P16P8 Resource Allocations ====
Device | Resource | Design | Part |
Resources | Available | Requirement | Utilization | Unused
======================|===========|=============|=============|==============
| | | |
Dedicated input pins | 10 | 4 | 4 | 6 ( 60 %)
Combinatorial inputs | 10 | 4 | 4 | 6 ( 60 %)
Registered inputs | - | 0 | - | -
| | | |
Dedicated output pins | 2 | 7 | 1 | 1 ( 50 %)
Bidirectional pins | 6 | 0 | 6 | 0 ( 0 %)
Combinatorial outputs | 8 | 7 | 7 | 1 ( 12 %)
Registered outputs | - | 0 | - | -
Two-input XOR | - | 0 | - | -
| | | |
Buried nodes | - | 0 | - | -
Buried registers | - | 0 | - | -
Buried combinatorials | - | 0 | - | -
Page 4
EZ-ABEL 4.30 - Device Utilization Chart Fri Jun 27 13:01:23 19;4
seven segment display decoder 1 Aug 1990
Walter Bright Data I/O Corp Redmond WA
==== P16P8 Product Terms Distribution ====
Signal | Pin | Terms | Terms | Terms
Name | Assigned | Used | Max | Unused
===============================|==========|=======|=======|=======
g | 19 | 3 | 7 | 4
f | 18 | 4 | 7 | 3
e | 17 | 3 | 7 | 4
d | 16 | 4 | 7 | 3
c | 15 | 3 | 7 | 4
b | 14 | 4 | 7 | 3
a | 13 | 3 | 7 | 4
==== List of Inputs/Feedbacks ====
Signal Name | Pin | Pin Type
============================== |==========|=========
D3 | 2 | INPUT
D2 | 3 | INPUT
D1 | 4 | INPUT
D0 | 5 | INPUT
Page 5
EZ-ABEL 4.30 - Device Utilization Chart Fri Jun 27 13:01:23 19;4
seven segment display decoder 1 Aug 1990
Walter Bright Data I/O Corp Redmond WA
==== P16P8 Unused Resources ====
Pin | Pin | Product | Flip-flop
Number | Type | Terms | Type
=======|========|=============|==========
1 | INPUT | - | -
6 | INPUT | - | -
7 | INPUT | - | -
8 | INPUT | - | -
9 | INPUT | - | -
11 | INPUT | - | -
12 | OUTPUT | NORMAL 7 | -
Page 6
EZ-ABEL 4.30 - Device Utilization Chart Fri Jun 27 13:01:23 19;4
seven segment display decoder 1 Aug 1990
Walter Bright Data I/O Corp Redmond WA
==== I/O Files ====
Module: 'bcd7'
Input files
===========
ABEL PLA file: bcd7.tt2
Vector file: bcd7.tmv
Device library: P16P8.dev
Output files
============
Report file: bcd7.doc
Programmer load file: bcd7.jed

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EZ-ABEL 4.32 Data I/O Corp. JEDEC file for: P16P8 V9.0
Created on: Fri Jun 27 13:01:23 19;4
seven segment display decoder 1 Aug 1990
Walter Bright Data I/O Corp Redmond WA
*
QP20* QF2056* QV16* F0*
X0*
NOTE Table of pin names and numbers*
NOTE PINS D3:2 D2:3 D1:4 D0:5 a:13 b:14 c:15 d:16 e:17 f:18 g:19*
L0000 11111111111111111111111111111111*
L0032 10111011101111111111111111111111*
L0064 10110111011101111111111111111111*
L0096 01110111101110111111111111111111*
L0256 11111111111111111111111111111111*
L0288 10111011011111111111111111111111*
L0320 10111111011101111111111111111111*
L0352 10111011111101111111111111111111*
L0384 01110111101101111111111111111111*
L0512 11111111111111111111111111111111*
L0544 10110111101111111111111111111111*
L0576 10111111111101111111111111111111*
L0608 11111011101101111111111111111111*
L0768 11111111111111111111111111111111*
L0800 11110111011101111111111111111111*
L0832 10111011101101111111111111111111*
L0864 01111011011110111111111111111111*
L0896 10110111101110111111111111111111*
L1024 11111111111111111111111111111111*
L1056 01110111111110111111111111111111*
L1088 01110111011111111111111111111111*
L1120 10111011011110111111111111111111*
L1280 11111111111111111111111111111111*
L1312 11111011111111111111111111111111*
L1344 10111111011101111111111111111111*
L1376 01111111101101111111111111111111*
L1408 10111111101110111111111111111111*
L1536 11111111111111111111111111111111*
L1568 01110111101101111111111111111111*
L1600 10111011101101111111111111111111*
L1632 10110111101110111111111111111111*
L2048 11111010*
V0001 X0000XXXXNXXLLLLLLHN*
V0002 X0001XXXXNXXHLLHHHHN*
V0003 X0010XXXXNXXLLHLLHLN*
V0004 X0011XXXXNXXLLLLHHLN*
V0005 X0100XXXXNXXHLLHHLLN*
V0006 X0101XXXXNXXLHLLHLLN*
V0007 X0110XXXXNXXLHLLLLLN*
V0008 X0111XXXXNXXLLLHHHHN*
V0009 X1000XXXXNXXLLLLLLLN*
V0010 X1001XXXXNXXLLLLHLLN*
V0011 X1010XXXXNXXLLLHLLLN*
V0012 X1011XXXXNXXLLLLLLLN*
V0013 X1100XXXXNXXLHHLLLHN*
V0014 X1101XXXXNXXHLLLLHLN*
V0015 X1110XXXXNXXLHHLLLLN*
V0016 X1111XXXXNXXLHHHLLLN*
C7840*
B9D1

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0001 |module BCD7
0002 |title 'seven segment display decoder 1 Aug 1990
0003 |Walter Bright Data I/O Corp Redmond WA'
0004 |" a
0005 |" --- BCD-to-seven-segment decoder similar to the 7449
0006 |" f| g |b
0007 |" --- segment identification
0008 |" e| d |c
0009 |" ---
0010 | bcd7 device 'P16P8';
0011 |
0012 | D3,D2,D1,D0 pin 2,3,4,5;
0013 | a,b,c,d,e,f,g pin 13,14,15,16,17,18,19 istype 'com';
0014 |
0015 | bcd = [D3,D2,D1,D0];
0016 | led = [a,b,c,d,e,f,g];
0017 |
0018 | ON,OFF = 0,1; " for common anode LEDs
0019 | L,H,X,Z = 0,1,.X.,.Z.;
0020 |@dcset
0021 |truth_table (bcd -> [ a , b , c , d , e , f , g ])
0022 | 0 -> [ ON, ON, ON, ON, ON, ON, OFF];
0023 | 1 -> [OFF, ON, ON, OFF, OFF, OFF, OFF];
0024 | 2 -> [ ON, ON, OFF, ON, ON, OFF, ON];
0025 | 3 -> [ ON, ON, ON, ON, OFF, OFF, ON];
0026 | 4 -> [OFF, ON, ON, OFF, OFF, ON, ON];
0027 | 5 -> [ ON, OFF, ON, ON, OFF, ON, ON];
0028 | 6 -> [ ON, OFF, ON, ON, ON, ON, ON];
0029 | 7 -> [ ON, ON, ON, OFF, OFF, OFF, OFF];
0030 | 8 -> [ ON, ON, ON, ON, ON, ON, ON];
0031 | 9 -> [ ON, ON, ON, ON, OFF, ON, ON];
0032 |
0033 |test_vectors (bcd -> [ a , b , c , d , e , f , g ])
0034 | 0 -> [ ON, ON, ON, ON, ON, ON, OFF];
0035 | 1 -> [OFF, ON, ON, OFF, OFF, OFF, OFF];
0036 | 2 -> [ ON, ON, OFF, ON, ON, OFF, ON];
0037 | 3 -> [ ON, ON, ON, ON, OFF, OFF, ON];
0038 | 4 -> [OFF, ON, ON, OFF, OFF, ON, ON];
0039 | 5 -> [ ON, OFF, ON, ON, OFF, ON, ON];
0040 | 6 -> [ ON, OFF, ON, ON, ON, ON, ON];
0041 | 7 -> [ ON, ON, ON, OFF, OFF, OFF, OFF];
0042 | 8 -> [ ON, ON, ON, ON, ON, ON, ON];
0043 | 9 -> [ ON, ON, ON, ON, OFF, ON, ON];
0044 | 10 -> [ X , X , X , X , X , X , X ];
0045 | 11 -> [ X , X , X , X , X , X , X ];
0046 | 12 -> [ X , X , X , X , X , X , X ];
0047 | 13 -> [ X , X , X , X , X , X , X ];
0048 | 14 -> [ X , X , X , X , X , X , X ];
0049 | 15 -> [ X , X , X , X , X , X , X ];
0050 |end

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Simulate EZ-ABEL 4.30 Date: Fri Jun 27 13:01:23 19;4
Fuse file: 'bcd7.jed' Vector file: 'bcd7.jed' Part: 'P16P8'
EZ-ABEL 4.32 Data I/O Corp. JEDEC file for: P16P8 V9.0
Created on: Fri Jun 27 13:01:23 19;4
seven segment display decoder 1 Aug 1990
Walter Bright Data I/O Corp Redmond WA
D D D D
3 2 1 0 a b c d e f g
V0001 0 0 0 0 L L L L L L H
V0002 0 0 0 1 H L L H H H H
V0003 0 0 1 0 L L H L L H L
V0004 0 0 1 1 L L L L H H L
V0005 0 1 0 0 H L L H H L L
V0006 0 1 0 1 L H L L H L L
V0007 0 1 1 0 L H L L L L L
V0008 0 1 1 1 L L L H H H H
V0009 1 0 0 0 L L L L L L L
V0010 1 0 0 1 L L L L H L L
V0011 1 0 1 0 L L L H L L L
V0012 1 0 1 1 L L L L L L L
V0013 1 1 0 0 L H H L L L H
V0014 1 1 0 1 H L L L L H L
V0015 1 1 1 0 L H H L L L L
V0016 1 1 1 1 L H H H L L L
16 out of 16 vectors passed.

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#$ TOOL EZ-ABEL 4.30
#$ MODULE BCD7
#$ TITLE seven segment display decoder 1 Aug 1990
#$ TITLE Walter Bright Data I/O Corp Redmond WA
S11;
D3 D2 D1 D0 -> a b c d e f g
$
0000->0000001;
0001->1001111;
0010->0010010;
0011->0000110;
0100->1001100;
0101->0100100;
0110->0100000;
0111->0001111;
1000->0000000;
1001->0000100;
1010->0001000;
1011->0000000;
1100->0110001;
1101->1000010;
1110->0110000;
1111->0111000;
$

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module BCD7
title 'seven segment display decoder 1 Aug 1990
Walter Bright Data I/O Corp Redmond WA'
" a
" --- BCD-to-seven-segment decoder similar to the 7449
" f| g |b
" --- segment identification
" e| d |c
" ---
bcd7 device 'P16P8';
D3,D2,D1,D0 pin 2,3,4,5;
a,b,c,d,e,f,g pin 13,14,15,16,17,18,19 istype 'com';
bcd = [D3,D2,D1,D0];
led = [a,b,c,d,e,f,g];
ON,OFF = 0,1; " for common anode LEDs
L,H,X,Z = 0,1,.X.,.Z.;
@dcset
truth_table (bcd -> [ a , b , c , d , e , f , g ])
0 -> [ ON, ON, ON, ON, ON, ON, OFF]; " 0
1 -> [OFF, ON, ON, OFF, OFF, OFF, OFF]; " 1
2 -> [ ON, ON, OFF, ON, ON, OFF, ON]; " 2
3 -> [ ON, ON, ON, ON, OFF, OFF, ON]; " 3
4 -> [OFF, ON, ON, OFF, OFF, ON, ON]; " 4
5 -> [ ON, OFF, ON, ON, OFF, ON, ON]; " 5
6 -> [ ON, OFF, ON, ON, ON, ON, ON]; " 6
7 -> [ ON, ON, ON, OFF, OFF, OFF, OFF]; " 7
8 -> [ ON, ON, ON, ON, ON, ON, ON]; " 8
9 -> [ ON, ON, ON, ON, OFF, ON, ON]; " 9
10 -> [ ON, ON, ON, OFF, ON, ON, ON]; " A
11 -> [ ON, ON, ON, ON, ON, ON, ON]; " B
12 -> [ ON, OFF, OFF, ON, ON, ON, OFF]; " C
13 -> [OFF, ON, ON, ON, ON, OFF, ON]; " d
14 -> [ ON, OFF, OFF, ON, ON, ON, ON]; " E
15 -> [ ON, OFF, OFF, OFF, ON, ON, ON]; " F
test_vectors (bcd -> [ a , b , c , d , e , f , g ])
0 -> [ ON, ON, ON, ON, ON, ON, OFF];
1 -> [OFF, ON, ON, OFF, OFF, OFF, OFF];
2 -> [ ON, ON, OFF, ON, ON, OFF, ON];
3 -> [ ON, ON, ON, ON, OFF, OFF, ON];
4 -> [OFF, ON, ON, OFF, OFF, ON, ON];
5 -> [ ON, OFF, ON, ON, OFF, ON, ON];
6 -> [ ON, OFF, ON, ON, ON, ON, ON];
7 -> [ ON, ON, ON, OFF, OFF, OFF, OFF];
8 -> [ ON, ON, ON, ON, ON, ON, ON];
9 -> [ ON, ON, ON, ON, OFF, ON, ON];
10 -> [ ON, ON, ON, OFF, ON, ON, ON];
11 -> [ ON, ON, ON, ON, ON, ON, ON];
12 -> [ ON, OFF, OFF, ON, ON, ON, OFF];
13 -> [OFF, ON, ON, ON, ON, OFF, ON];
14 -> [ ON, OFF, OFF, ON, ON, ON, ON];
15 -> [ ON, OFF, OFF, OFF, ON, ON, ON];
end

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#$ SOURCEFILE BCD7_LCD.abl
#$ LISTFILE BCD7_LCD.lst
#$ MODULE bcd7
#$ DEVICE 'P16P8' ASSIGNED
#$ PLAFILE bcd7.tt1
#$ JEDECFILE bcd7

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0001 |module BCD7
0002 |title 'seven segment display decoder 1 Aug 1990
0003 |Walter Bright Data I/O Corp Redmond WA'
0004 |" a
0005 |" --- BCD-to-seven-segment decoder similar to the 7449
0006 |" f| g |b
0007 |" --- segment identification
0008 |" e| d |c
0009 |" ---
0010 | bcd7 device 'P16P8';
0011 |
0012 | D3,D2,D1,D0 pin 2,3,4,5;
0013 | a,b,c,d,e,f,g pin 13,14,15,16,17,18,19 istype 'com';
0014 |
0015 | bcd = [D3,D2,D1,D0];
0016 | led = [a,b,c,d,e,f,g];
0017 |
0018 | ON,OFF = 0,1; " for common anode LEDs
0019 | L,H,X,Z = 0,1,.X.,.Z.;
0020 |@dcset
0021 |truth_table (bcd -> [ a , b , c , d , e , f , g ])
0022 | 0 -> [ ON, ON, ON, ON, ON, ON, OFF]; " 0
0023 | 1 -> [OFF, ON, ON, OFF, OFF, OFF, OFF]; " 1
0024 | 2 -> [ ON, ON, OFF, ON, ON, OFF, ON]; " 2
0025 | 3 -> [ ON, ON, ON, ON, OFF, OFF, ON]; " 3
0026 | 4 -> [OFF, ON, ON, OFF, OFF, ON, ON]; " 4
0027 | 5 -> [ ON, OFF, ON, ON, OFF, ON, ON]; " 5
0028 | 6 -> [ ON, OFF, ON, ON, ON, ON, ON]; " 6
0029 | 7 -> [ ON, ON, ON, OFF, OFF, OFF, OFF]; " 7
0030 | 8 -> [ ON, ON, ON, ON, ON, ON, ON]; " 8
0031 | 9 -> [ ON, ON, ON, ON, OFF, ON, ON]; " 9
0032 | 10 -> [ ON, ON, ON, OFF, ON, ON, ON]; " A
0033 | 11 -> [ ON, ON, ON, ON, ON, ON, ON]; " B
0034 | 12 -> [ ON, OFF, OFF, ON, ON, ON, OFF]; " C
0035 | 13 -> [OFF, ON, ON, ON, ON, OFF, ON]; " d
0036 | 14 -> [ ON, OFF, OFF, ON, ON, ON, ON]; " E
0037 | 15 -> [ ON, OFF, OFF, OFF, ON, ON, ON]; " F
0038 |
0039 |test_vectors (bcd -> [ a , b , c , d , e , f , g ])
0040 | 0 -> [ ON, ON, ON, ON, ON, ON, OFF];
0041 | 1 -> [OFF, ON, ON, OFF, OFF, OFF, OFF];
0042 | 2 -> [ ON, ON, OFF, ON, ON, OFF, ON];
0043 | 3 -> [ ON, ON, ON, ON, OFF, OFF, ON];
0044 | 4 -> [OFF, ON, ON, OFF, OFF, ON, ON];
0045 | 5 -> [ ON, OFF, ON, ON, OFF, ON, ON];
0046 | 6 -> [ ON, OFF, ON, ON, ON, ON, ON];
0047 | 7 -> [ ON, ON, ON, OFF, OFF, OFF, OFF];
0048 | 8 -> [ ON, ON, ON, ON, ON, ON, ON];
0049 | 9 -> [ ON, ON, ON, ON, OFF, ON, ON];
0050 | 10 -> [ ON, ON, ON, OFF, ON, ON, ON];
0051 | 11 -> [ ON, ON, ON, ON, ON, ON, ON];
0052 | 12 -> [ ON, OFF, OFF, ON, ON, ON, OFF];
0053 | 13 -> [OFF, ON, ON, ON, ON, OFF, ON];
0054 | 14 -> [ ON, OFF, OFF, ON, ON, ON, ON];
0055 | 15 -> [ ON, OFF, OFF, OFF, ON, ON, ON];
0056 |end

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module BINBCD
title 'comparator and binary to bcd decoder for Blackjack Machine
Michael Holley Data I/O Corp 12 Oct 1992'
" The 5 -bit binary (0 - 31) score is converted into two BCD outputs.
" The interger division '/' and the modulus operator '%' are used to
" extract the individual digits from the two digit score.
" 'Score % 10' will yield the 'units' and
" 'Score / 10' will yield the 'tens'
"
" The 'GT16' and 'LT22' outputs are for the state machine controller.
binbcd device 'P16L8';
S4,S3,S2,S1,S0 pin 5,4,3,2,1;
score = [S4,S3,S2,S1,S0];
LT22,GT16 pin 12,13 istype 'com';
D5,D4 pin 14,15 istype 'com';
bcd2 = [D5,D4];
D3,D2,D1,D0 pin 16,17,18,19 istype 'com';
bcd1 = [D3,D2,D1,D0];
" Digit separation macros
binary = 0; "scratch variable
clear macro (a) {@const ?a=0};
inc macro (a) {@const ?a=?a+1;};
equations
LT22 = (score < 22); "Bust
GT16 = (score > 16); "Hit / Stand
test_vectors ( score -> [GT16,LT22])
1 -> [ 0 , 1 ];
6 -> [ 0 , 1 ];
8 -> [ 0 , 1 ];
16 -> [ 0 , 1 ];
17 -> [ 1 , 1 ];
18 -> [ 1 , 1 ];
20 -> [ 1 , 1 ];
21 -> [ 1 , 1 ];
22 -> [ 1 , 0 ];
23 -> [ 1 , 0 ];
24 -> [ 1 , 0 ];
@page
truth_table ( score -> [bcd2,bcd1])
0 -> [ 0 , 0 ];
1 -> [ 0 , 1 ];
2 -> [ 0 , 2 ];
3 -> [ 0 , 3 ];
4 -> [ 0 , 4 ];
5 -> [ 0 , 5 ];
6 -> [ 0 , 6 ];
7 -> [ 0 , 7 ];
8 -> [ 0 , 8 ];
9 -> [ 0 , 9 ];
10 -> [ 1 , 0 ];
11 -> [ 1 , 1 ];
12 -> [ 1 , 2 ];
13 -> [ 1 , 3 ];
14 -> [ 1 , 4 ];
15 -> [ 1 , 5 ];
16 -> [ 1 , 6 ];
17 -> [ 1 , 7 ];
18 -> [ 1 , 8 ];
19 -> [ 1 , 9 ];
20 -> [ 2 , 0 ];
21 -> [ 2 , 1 ];
22 -> [ 2 , 2 ];
23 -> [ 2 , 3 ];
24 -> [ 2 , 4 ];
25 -> [ 2 , 5 ];
26 -> [ 2 , 6 ];
27 -> [ 2 , 7 ];
28 -> [ 2 , 8 ];
29 -> [ 2 , 9 ];
30 -> [ 3 , 0 ];
31 -> [ 3 , 1 ];
" This truth table could be replaced with the following macro.
" clear(binary);
" @repeat 32 {
" binary -> [binary/10,binary%10]; inc(binary);}
"
"
" The test vectors will demonstrate the use of the macro.
"
test_vectors ( score -> [bcd2,bcd1])
clear(binary);
@repeat 32 {
binary -> [binary/10,binary%10]; inc(binary);}
end

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#$ SOURCEFILE BINBCD.abl
#$ LISTFILE BINBCD.lst
#$ MODULE binbcd
#$ DEVICE 'P16L8' ASSIGNED
#$ PLAFILE binbcd.tt1
#$ JEDECFILE binbcd

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Page 1
EZ-ABEL 4.30 - Device Utilization Chart Mon Apr 7 14:55:02 19;4
comparator and binary to bcd decoder for Blackjack Machine
Michael Holley Data I/O Corp 12 Oct 1992
==== P16L8 Programmed Logic ====
LT22 = !( S4 & S3
# S4 & S2 & S1 );
GT16 = !( !S4
# !S3 & !S2 & !S1 & !S0 );
D0 = !( !S0 );
D1 = !( !S4 & S3 & !S2
# S3 & S2 & S1
# S4 & !S3 & !S2 & S1
# S4 & S3 & !S1
# !S4 & !S3 & !S1
# !S3 & S2 & !S1 );
D2 = !( S4 & S2
# !S4 & !S2
# !S3 & !S2 & S1
# !S4 & S3 & !S1 );
D3 = !( !S4 & S2
# S4 & S3 & !S2
# !S4 & S1
# S2 & S1
# !S3 & !S1 );
D4 = !( !S4 & !S3
# !S3 & S2
# S4 & S3 & !S2
# S4 & S3 & !S1
# !S4 & !S2 & !S1 );
D5 = !( !S4
# !S3 & !S2 );
Page 2
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comparator and binary to bcd decoder for Blackjack Machine
Michael Holley Data I/O Corp 12 Oct 1992
==== P16L8 Chip Diagram ====
P16L8
+---------\ /---------+
| \ / |
| ----- |
S0 | 1 20 | Vcc
| |
S1 | 2 19 | !D0
| |
S2 | 3 18 | !D1
| |
S3 | 4 17 | !D2
| |
S4 | 5 16 | !D3
| |
| 6 15 | !D4
| |
| 7 14 | !D5
| |
| 8 13 | !GT16
| |
| 9 12 | !LT22
| |
GND | 10 11 |
| |
| |
`---------------------------'
SIGNATURE: N/A
Page 3
EZ-ABEL 4.30 - Device Utilization Chart Mon Apr 7 14:55:02 19;4
comparator and binary to bcd decoder for Blackjack Machine
Michael Holley Data I/O Corp 12 Oct 1992
==== P16L8 Resource Allocations ====
Device | Resource | Design | Part |
Resources | Available | Requirement | Utilization | Unused
======================|===========|=============|=============|==============
| | | |
Dedicated input pins | 10 | 5 | 5 | 5 ( 50 %)
Combinatorial inputs | 10 | 5 | 5 | 5 ( 50 %)
Registered inputs | - | 0 | - | -
| | | |
Dedicated output pins | 2 | 8 | 2 | 0 ( 0 %)
Bidirectional pins | 6 | 0 | 6 | 0 ( 0 %)
Combinatorial outputs | 8 | 8 | 8 | 0 ( 0 %)
Registered outputs | - | 0 | - | -
Two-input XOR | - | 0 | - | -
| | | |
Buried nodes | - | 0 | - | -
Buried registers | - | 0 | - | -
Buried combinatorials | - | 0 | - | -
Page 4
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comparator and binary to bcd decoder for Blackjack Machine
Michael Holley Data I/O Corp 12 Oct 1992
==== P16L8 Product Terms Distribution ====
Signal | Pin | Terms | Terms | Terms
Name | Assigned | Used | Max | Unused
===============================|==========|=======|=======|=======
LT22 | 12 | 2 | 7 | 5
GT16 | 13 | 2 | 7 | 5
D0 | 19 | 1 | 7 | 6
D1 | 18 | 6 | 7 | 1
D2 | 17 | 4 | 7 | 3
D3 | 16 | 5 | 7 | 2
D4 | 15 | 5 | 7 | 2
D5 | 14 | 2 | 7 | 5
==== List of Inputs/Feedbacks ====
Signal Name | Pin | Pin Type
============================== |==========|=========
S4 | 5 | INPUT
S3 | 4 | INPUT
S2 | 3 | INPUT
S1 | 2 | INPUT
S0 | 1 | INPUT
Page 5
EZ-ABEL 4.30 - Device Utilization Chart Mon Apr 7 14:55:02 19;4
comparator and binary to bcd decoder for Blackjack Machine
Michael Holley Data I/O Corp 12 Oct 1992
==== P16L8 Unused Resources ====
Pin | Pin | Product | Flip-flop
Number | Type | Terms | Type
=======|========|=============|==========
6 | INPUT | - | -
7 | INPUT | - | -
8 | INPUT | - | -
9 | INPUT | - | -
11 | INPUT | - | -
Page 6
EZ-ABEL 4.30 - Device Utilization Chart Mon Apr 7 14:55:02 19;4
comparator and binary to bcd decoder for Blackjack Machine
Michael Holley Data I/O Corp 12 Oct 1992
==== I/O Files ====
Module: 'binbcd'
Input files
===========
ABEL PLA file: binbcd.tt2
Vector file: binbcd.tmv
Device library: P16L8.dev
Output files
============
Report file: binbcd.doc
Programmer load file: binbcd.jed

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EZ-ABEL 4.32 Data I/O Corp. JEDEC file for: P16L8 V9.0
Created on: Mon Apr 7 14:55:02 19;4
comparator and binary to bcd decoder for Blackjack Machine
Michael Holley Data I/O Corp 12 Oct 1992
*
QP20* QF2048* QV43* F0*
X0*
NOTE Table of pin names and numbers*
NOTE PINS S4:5 S3:4 S2:3 S1:2 S0:1 LT22:12 GT16:13 D5:14 D4:15 D3:16*
NOTE PINS D2:17 D1:18 D0:19*
L0000 11111111111111111111111111111111*
L0032 11101111111111111111111111111111*
L0256 11111111111111111111111111111111*
L0288 11111011011110111111111111111111*
L0320 01110111011111111111111111111111*
L0352 01111011101101111111111111111111*
L0384 10111111011101111111111111111111*
L0416 10111111101110111111111111111111*
L0448 10110111101111111111111111111111*
L0512 11111111111111111111111111111111*
L0544 11110111111101111111111111111111*
L0576 11111011111110111111111111111111*
L0608 01111011101111111111111111111111*
L0640 10111111011110111111111111111111*
L0768 11111111111111111111111111111111*
L0800 11110111111110111111111111111111*
L0832 11111011011101111111111111111111*
L0864 01111111111110111111111111111111*
L0896 01110111111111111111111111111111*
L0928 10111111101111111111111111111111*
L1024 11111111111111111111111111111111*
L1056 11111111101110111111111111111111*
L1088 11110111101111111111111111111111*
L1120 11111011011101111111111111111111*
L1152 10111111011101111111111111111111*
L1184 10111011111110111111111111111111*
L1280 11111111111111111111111111111111*
L1312 11111111111110111111111111111111*
L1344 11111011101111111111111111111111*
L1536 11111111111111111111111111111111*
L1568 11111111111110111111111111111111*
L1600 10101011101111111111111111111111*
L1792 11111111111111111111111111111111*
L1824 11111111011101111111111111111111*
L1856 01110111111101111111111111111111*
V0001 10000XXXXNXHLXXXXXXN*
V0002 01100XXXXNXHLXXXXXXN*
V0003 00010XXXXNXHLXXXXXXN*
V0004 00001XXXXNXHLXXXXXXN*
V0005 10001XXXXNXHHXXXXXXN*
V0006 01001XXXXNXHHXXXXXXN*
V0007 00101XXXXNXHHXXXXXXN*
V0008 10101XXXXNXHHXXXXXXN*
V0009 01101XXXXNXLHXXXXXXN*
V0010 11101XXXXNXLHXXXXXXN*
V0011 00011XXXXNXLHXXXXXXN*
V0012 00000XXXXNXXXLLLLLLN*
V0013 10000XXXXNXXXLLLLLHN*
V0014 01000XXXXNXXXLLLLHLN*
V0015 11000XXXXNXXXLLLLHHN*
V0016 00100XXXXNXXXLLLHLLN*
V0017 10100XXXXNXXXLLLHLHN*
V0018 01100XXXXNXXXLLLHHLN*
V0019 11100XXXXNXXXLLLHHHN*
V0020 00010XXXXNXXXLLHLLLN*
V0021 10010XXXXNXXXLLHLLHN*
V0022 01010XXXXNXXXLHLLLLN*
V0023 11010XXXXNXXXLHLLLHN*
V0024 00110XXXXNXXXLHLLHLN*
V0025 10110XXXXNXXXLHLLHHN*
V0026 01110XXXXNXXXLHLHLLN*
V0027 11110XXXXNXXXLHLHLHN*
V0028 00001XXXXNXXXLHLHHLN*
V0029 10001XXXXNXXXLHLHHHN*
V0030 01001XXXXNXXXLHHLLLN*
V0031 11001XXXXNXXXLHHLLHN*
V0032 00101XXXXNXXXHLLLLLN*
V0033 10101XXXXNXXXHLLLLHN*
V0034 01101XXXXNXXXHLLLHLN*
V0035 11101XXXXNXXXHLLLHHN*
V0036 00011XXXXNXXXHLLHLLN*
V0037 10011XXXXNXXXHLLHLHN*
V0038 01011XXXXNXXXHLLHHLN*
V0039 11011XXXXNXXXHLLHHHN*
V0040 00111XXXXNXXXHLHLLLN*
V0041 10111XXXXNXXXHLHLLHN*
V0042 01111XXXXNXXXHHLLLLN*
V0043 11111XXXXNXXXHHLLLHN*
C87E4*
A5F7

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0001 |module BINBCD
0002 |title 'comparator and binary to bcd decoder for Blackjack Machine
0003 |Michael Holley Data I/O Corp 12 Oct 1992'
0004 |
0005 |" The 5 -bit binary (0 - 31) score is converted into two BCD outputs.
0006 |" The interger division '/' and the modulus operator '%' are used to
0007 |" extract the individual digits from the two digit score.
0008 |" 'Score % 10' will yield the 'units' and
0009 |" 'Score / 10' will yield the 'tens'
0010 |"
0011 |" The 'GT16' and 'LT22' outputs are for the state machine controller.
0012 |
0013 | binbcd device 'P16L8';
0014 |
0015 | S4,S3,S2,S1,S0 pin 5,4,3,2,1;
0016 | score = [S4,S3,S2,S1,S0];
0017 |
0018 | LT22,GT16 pin 12,13 istype 'com';
0019 |
0020 | D5,D4 pin 14,15 istype 'com';
0021 | bcd2 = [D5,D4];
0022 |
0023 | D3,D2,D1,D0 pin 16,17,18,19 istype 'com';
0024 | bcd1 = [D3,D2,D1,D0];
0025 |
0026 |" Digit separation macros
0027 | binary = 0; "scratch variable
0028 | clear macro (a) {@const ?a=0};
0029 | inc macro (a) {@const ?a=?a+1;};
0030 |
0031 |equations
0032 | LT22 = (score < 22); "Bust
0033 | GT16 = (score > 16); "Hit / Stand
0034 |
0035 |test_vectors ( score -> [GT16,LT22])
0036 | 1 -> [ 0 , 1 ];
0037 | 6 -> [ 0 , 1 ];
0038 | 8 -> [ 0 , 1 ];
0039 | 16 -> [ 0 , 1 ];
0040 | 17 -> [ 1 , 1 ];
0041 | 18 -> [ 1 , 1 ];
0042 | 20 -> [ 1 , 1 ];
0043 | 21 -> [ 1 , 1 ];
0044 | 22 -> [ 1 , 0 ];
0045 | 23 -> [ 1 , 0 ];
0046 | 24 -> [ 1 , 0 ];
0047 |@page
0048 |truth_table ( score -> [bcd2,bcd1])
0049 | 0 -> [ 0 , 0 ];
0050 | 1 -> [ 0 , 1 ];
0051 | 2 -> [ 0 , 2 ];
0052 | 3 -> [ 0 , 3 ];
0053 | 4 -> [ 0 , 4 ];
0054 | 5 -> [ 0 , 5 ];
0055 | 6 -> [ 0 , 6 ];
0056 | 7 -> [ 0 , 7 ];
0057 | 8 -> [ 0 , 8 ];
0058 | 9 -> [ 0 , 9 ];
0059 | 10 -> [ 1 , 0 ];
0060 | 11 -> [ 1 , 1 ];
0061 | 12 -> [ 1 , 2 ];
0062 | 13 -> [ 1 , 3 ];
0063 | 14 -> [ 1 , 4 ];
0064 | 15 -> [ 1 , 5 ];
0065 | 16 -> [ 1 , 6 ];
0066 | 17 -> [ 1 , 7 ];
0067 | 18 -> [ 1 , 8 ];
0068 | 19 -> [ 1 , 9 ];
0069 | 20 -> [ 2 , 0 ];
0070 | 21 -> [ 2 , 1 ];
0071 | 22 -> [ 2 , 2 ];
0072 | 23 -> [ 2 , 3 ];
0073 | 24 -> [ 2 , 4 ];
0074 | 25 -> [ 2 , 5 ];
0075 | 26 -> [ 2 , 6 ];
0076 | 27 -> [ 2 , 7 ];
0077 | 28 -> [ 2 , 8 ];
0078 | 29 -> [ 2 , 9 ];
0079 | 30 -> [ 3 , 0 ];
0080 | 31 -> [ 3 , 1 ];
0081 |
0082 |" This truth table could be replaced with the following macro.
0083 |" clear(binary);
0084 |" @repeat 32 {
0085 |" binary -> [binary/10,binary%10]; inc(binary);}
0086 |"
0087 |"
0088 |" The test vectors will demonstrate the use of the macro.
0089 |"
0090 |test_vectors ( score -> [bcd2,bcd1])
0091 | clear(binary);
0092 | @repeat 32 {
0093 | binary -> [binary/10,binary%10]; inc(binary);}
0094 |end

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Simulate EZ-ABEL 4.30 Date: Mon Apr 7 14:55:02 19;4
Fuse file: 'binbcd.jed' Vector file: 'binbcd.jed' Part: 'P16L8'
EZ-ABEL 4.32 Data I/O Corp. JEDEC file for: P16L8 V9.0
Created on: Mon Apr 7 14:55:02 19;4
comparator and binary to bcd decoder for Blackjack Machine
Michael Holley Data I/O Corp 12 Oct 1992
L G
T T
S S S S S 2 1 D D D D D D
0 1 2 3 4 2 6 5 4 3 2 1 0
V0001 1 0 0 0 0 H L L L L L L H
V0002 0 1 1 0 0 H L L L L H H L
V0003 0 0 0 1 0 H L L L H L L L
V0004 0 0 0 0 1 H L L H L H H L
V0005 1 0 0 0 1 H H L H L H H H
V0006 0 1 0 0 1 H H L H H L L L
V0007 0 0 1 0 1 H H H L L L L L
V0008 1 0 1 0 1 H H H L L L L H
V0009 0 1 1 0 1 L H H L L L H L
V0010 1 1 1 0 1 L H H L L L H H
V0011 0 0 0 1 1 L H H L L H L L
V0012 0 0 0 0 0 H L L L L L L L
V0013 1 0 0 0 0 H L L L L L L H
V0014 0 1 0 0 0 H L L L L L H L
V0015 1 1 0 0 0 H L L L L L H H
V0016 0 0 1 0 0 H L L L L H L L
V0017 1 0 1 0 0 H L L L L H L H
V0018 0 1 1 0 0 H L L L L H H L
V0019 1 1 1 0 0 H L L L L H H H
V0020 0 0 0 1 0 H L L L H L L L
V0021 1 0 0 1 0 H L L L H L L H
V0022 0 1 0 1 0 H L L H L L L L
V0023 1 1 0 1 0 H L L H L L L H
V0024 0 0 1 1 0 H L L H L L H L
V0025 1 0 1 1 0 H L L H L L H H
V0026 0 1 1 1 0 H L L H L H L L
V0027 1 1 1 1 0 H L L H L H L H
V0028 0 0 0 0 1 H L L H L H H L
V0029 1 0 0 0 1 H H L H L H H H
V0030 0 1 0 0 1 H H L H H L L L
V0031 1 1 0 0 1 H H L H H L L H
V0032 0 0 1 0 1 H H H L L L L L
V0033 1 0 1 0 1 H H H L L L L H
V0034 0 1 1 0 1 L H H L L L H L
V0035 1 1 1 0 1 L H H L L L H H
V0036 0 0 0 1 1 L H H L L H L L
V0037 1 0 0 1 1 L H H L L H L H
V0038 0 1 0 1 1 L H H L L H H L
V0039 1 1 0 1 1 L H H L L H H H
V0040 0 0 1 1 1 L H H L H L L L
V0041 1 0 1 1 1 L H H L H L L H
V0042 0 1 1 1 1 L H H H L L L L
V0043 1 1 1 1 1 L H H H L L L H
43 out of 43 vectors passed.

55
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#$ TOOL EZ-ABEL 4.30
#$ MODULE BINBCD
#$ TITLE comparator and binary to bcd decoder for Blackjack Machine
#$ TITLE Michael Holley Data I/O Corp 12 Oct 1992
S7;
S4 S3 S2 S1 S0 -> GT16 LT22
$
00001->01;
00110->01;
01000->01;
10000->01;
10001->11;
10010->11;
10100->11;
10101->11;
10110->10;
10111->10;
11000->10;
$
S11;
S4 S3 S2 S1 S0 -> D5 D4 D3 D2 D1 D0
$
00000->000000;
00001->000001;
00010->000010;
00011->000011;
00100->000100;
00101->000101;
00110->000110;
00111->000111;
01000->001000;
01001->001001;
01010->010000;
01011->010001;
01100->010010;
01101->010011;
01110->010100;
01111->010101;
10000->010110;
10001->010111;
10010->011000;
10011->011001;
10100->100000;
10101->100001;
10110->100010;
10111->100011;
11000->100100;
11001->100101;
11010->100110;
11011->100111;
11100->101000;
11101->101001;
11110->110000;
11111->110001;
$

BIN
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BIN
trunk/workspace/01_EasyAbel/AHDL/BINBCD.TT2 Normal file
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module BJACK
title 'BlackJack state machine controller
Michael Holley Data I/O Corp. 12 Oct 1992'
bjack device 'P16R6';
"Inputs
Clk,ClkIN pin 1,2; "System clock
GT16,LT22 pin 3,4; "Score less than 17 and 22
is_Ace pin 5; "Card is ace
Restart pin 6; "Restart game
CardIn,CardOut pin 7,8; "Card present switches
Ena pin 11;
Sensor = [CardIn,CardOut];
_In = [ 0 , 1 ];
InOut = [ 1 , 1 ];
Out = [ 1 , 0 ];
"Outputs
AddClk pin 12; "Adder clock
Add10 pin 13; "Input Mux control
Sub10 pin 14; "Input Mux control
Q2,Q1,Q0 pin 15,16,17;
Ace pin 18; "Ace Memory
High,Low = 1,0;
H,L,C,X = 1,0,.C.,.X.; "test vector charactors
AddClk istype 'com';
Ace istype 'invert,reg';
Add10,Sub10,Q2,Q1,Q0 istype 'invert,reg';
Qstate = [Add10,Sub10,Q2,Q1,Q0];
Clear = [ 1 , 1 , 1, 1, 1];
ShowHit = [ 1 , 1 , 1, 1, 0];
AddCard = [ 1 , 1 , 0, 0, 0];
Add_10 = [ 0 , 1 , 0, 0, 0];
Wait = [ 1 , 1 , 0, 0, 1];
Test_17 = [ 1 , 1 , 0, 1, 0];
Test_22 = [ 1 , 1 , 0, 1, 1];
ShowStand = [ 1 , 1 , 1, 0, 0];
ShowBust = [ 1 , 1 , 1, 0, 1];
Sub_10 = [ 1 , 0 , 0, 0, 1];
Zero = [ 0 , 0 , 0, 0, 0];
equations
[Qstate,Ace].clk = Clk;
[Qstate,Ace].oe = !Ena;
@page
@dcset
state_diagram Qstate
State Clear: AddClk = !ClkIN;
Ace := Low;
if (Restart==Low) then Clear else ShowHit;
State ShowHit: AddClk = Low;
Ace := Ace.fb;
if (CardIn==Low) then AddCard else ShowHit;
State AddCard: AddClk = !ClkIN;
Ace := Ace.fb;
if (is_Ace & !Ace.fb) then Add_10 else Wait;
State Add_10: AddClk = !ClkIN;
Ace := High;
goto Wait;
State Wait: AddClk = Low;
Ace := Ace.fb;
if (CardOut==Low) then Test_17 else Wait;
State Test_17: AddClk = Low;
Ace := Ace.fb;
if !GT16 then ShowHit else Test_22;
State Test_22: AddClk = Low;
Ace := Ace.fb;
case LT22 : ShowStand;
!LT22 & !Ace.fb : ShowBust;
!LT22 & Ace.fb : Sub_10;
endcase;
State Sub_10: AddClk = !ClkIN;
Ace := Low;
goto Test_17;
State ShowBust: AddClk = Low;
Ace := Ace.fb;
if (Restart==Low) then Clear else ShowBust;
State ShowStand: AddClk = Low;
Ace := Ace.fb;
if (Restart==Low) then Clear else ShowStand;
State Zero: goto Clear;
@page
test_vectors 'Assume two cards that total between 16 and 21'
([Ena,Clk,ClkIN,GT16,LT22,is_Ace,Restart,Sensor] -> [Ace,Qstate,AddClk])
[ L , C , L , L , H , L , L , Out ] -> [ X ,Clear , H ];" 1
[ L , C , L , L , H , L , L , Out ] -> [ L ,Clear , H ];" 2
[ L , C , L , L , H , L , H , Out ] -> [ L ,ShowHit , L ];" 3
[ L , C , L , L , H , L , H ,InOut ] -> [ L ,ShowHit , L ];" 4
[ L , C , L , L , H , L , H , _In ] -> [ L ,AddCard , H ];" 5
[ L , C , L , L , H , L , H , _In ] -> [ L ,Wait , L ];" 6
[ L , C , L , L , H , L , H ,InOut ] -> [ L ,Wait , L ];" 7
[ L , C , L , L , H , L , H , Out ] -> [ L ,Test_17 , L ];" 8
[ L , C , L , L , H , L , H , Out ] -> [ L ,ShowHit , L ];" 9
[ L , C , L , L , H , L , H , Out ] -> [ L ,ShowHit , L ];" 10
[ L , C , L , L , H , L , H , _In ] -> [ L ,AddCard , H ];" 11
[ L , C , L , H , H , L , H , _In ] -> [ L ,Wait , L ];" 12
[ L , C , L , H , H , L , H ,InOut ] -> [ L ,Wait , L ];" 13
[ L , C , L , H , H , L , H , Out ] -> [ L ,Test_17 , L ];" 14
[ L , C , L , H , H , L , H , Out ] -> [ L ,Test_22 , L ];" 15
[ L , C , L , H , H , L , H , Out ] -> [ L ,ShowStand, L ];" 16
[ L , C , L , H , H , L , H , Out ] -> [ L ,ShowStand, L ];" 17
[ L , C , L , H , H , L , L , Out ] -> [ L ,Clear , H ];" 18
test_vectors 'Assume 2 Aces and another card that total between 16 and 21'
([Ena,Clk,ClkIN,GT16,LT22,is_Ace,Restart,Sensor] -> [Ace,Qstate,AddClk])
[ L , C , L , L , H , L , L , Out ] -> [ L ,Clear , H ];" 19
[ L , C , L , L , H , L , H , Out ] -> [ L ,ShowHit , L ];" 20
[ L , C , L , L , H , H , H ,InOut ] -> [ L ,ShowHit , L ];
[ L , C , L , L , H , H , H , _In ] -> [ L ,AddCard , H ];
[ L , C , L , L , H , H , H , _In ] -> [ L ,Add_10 , H ];
[ L , C , L , L , H , H , H , _In ] -> [ H ,Wait , L ];
[ L , C , L , L , H , L , H ,InOut ] -> [ H ,Wait , L ];
[ L , C , L , L , H , L , H , Out ] -> [ H ,Test_17 , L ];
[ L , C , L , L , H , L , H , Out ] -> [ H ,ShowHit , L ];
[ L , C , L , L , H , L , H , Out ] -> [ H ,ShowHit , L ];
[ L , C , L , L , H , H , H , _In ] -> [ H ,AddCard , H ];
[ L , C , L , L , H , H , H , _In ] -> [ H ,Wait , L ];
[ L , C , L , L , H , L , H ,InOut ] -> [ H ,Wait , L ];
[ L , C , L , L , H , L , H , Out ] -> [ H ,Test_17 , L ];
[ L , C , L , L , H , L , H , Out ] -> [ H ,ShowHit , L ];
[ L , C , L , L , H , L , H , Out ] -> [ H ,ShowHit , L ];
[ L , C , L , L , H , L , H , _In ] -> [ H ,AddCard , H ];
[ L , C , L , H , H , L , H , _In ] -> [ H ,Wait , L ];
[ L , C , L , H , H , L , H ,InOut ] -> [ H ,Wait , L ];
[ L , C , L , H , H , L , H , Out ] -> [ H ,Test_17 , L ];
[ L , C , L , H , H , L , H , Out ] -> [ H ,Test_22 , L ];
[ L , C , L , H , H , L , H , Out ] -> [ H ,ShowStand, L ];
[ L , C , L , H , H , L , H , Out ] -> [ H ,ShowStand, L ];
[ L , C , L , H , H , L , L , Out ] -> [ H ,Clear , H ];
@page
test_vectors 'Assume an Ace and 2 cards that total between 16 and 21'
([Ena,Clk,ClkIN,GT16,LT22,is_Ace,Restart,Sensor] -> [Ace,Qstate,AddClk])
[ L , C , L , L , H , L , L , Out ] -> [ L ,Clear , H ];
[ L , C , L , L , H , L , H , Out ] -> [ L ,ShowHit , L ];
[ L , C , L , L , H , H , H ,InOut ] -> [ L ,ShowHit , L ];
[ L , C , L , L , H , H , H , _In ] -> [ L ,AddCard , H ];
[ L , C , L , L , H , H , H , _In ] -> [ L ,Add_10 , H ];
[ L , C , L , L , H , H , H , _In ] -> [ H ,Wait , L ];
[ L , C , L , L , H , L , H ,InOut ] -> [ H ,Wait , L ];
[ L , C , L , L , H , L , H , Out ] -> [ H ,Test_17 , L ];
[ L , C , L , L , H , L , H , Out ] -> [ H ,ShowHit , L ];
[ L , C , L , L , H , L , H , Out ] -> [ H ,ShowHit , L ];
[ L , C , L , L , H , L , H , _In ] -> [ H ,AddCard , H ];
[ L , C , L , L , H , L , H , _In ] -> [ H ,Wait , L ];
[ L , C , L , L , H , L , H ,InOut ] -> [ H ,Wait , L ];
[ L , C , L , L , H , L , H , Out ] -> [ H ,Test_17 , L ];
[ L , C , L , L , H , L , H , Out ] -> [ H ,ShowHit , L ];
[ L , C , L , L , H , L , H , Out ] -> [ H ,ShowHit , L ];
[ L , C , L , L , H , L , H , _In ] -> [ H ,AddCard , H ];
[ L , C , L , H , L , L , H , _In ] -> [ H ,Wait , L ];
[ L , C , L , H , L , L , H ,InOut ] -> [ H ,Wait , L ];
[ L , C , L , H , L , L , H , Out ] -> [ H ,Test_17 , L ];
[ L , C , L , H , L , L , H , Out ] -> [ H ,Test_22 , L ];
[ L , C , L , H , L , L , H , Out ] -> [ H ,Sub_10 , H ];
[ L , C , L , H , H , L , H , Out ] -> [ L ,Test_17 , L ];
[ L , C , L , H , H , L , H , Out ] -> [ L ,Test_22 , L ];
[ L , C , L , H , H , L , H , Out ] -> [ L ,ShowStand, L ];
[ L , C , L , H , H , L , H , Out ] -> [ L ,ShowStand, L ];
[ L , C , L , H , H , L , L , Out ] -> [ L ,Clear , H ];
end

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module CNT10P
title 'decimal counter
Note: preload the data on pins into the registers
Denny Siu Data I/O Corp 9 Aug 1990'
cnt10p device 'P16R4';
Clk,Clr,OE pin 1,2,11;
Q3,Q2,Q1,Q0 pin 14,15,16,17 istype 'reg_D,invert';
Ck,X,Z,P = .C. , .X., .Z., .P.;
" Counter States
S0 = ^b1111; S4 = ^b1011; S8 = ^b0111; S12= ^b0011;
S1 = ^b1110; S5 = ^b1010; S9 = ^b0110; S13= ^b0010;
S2 = ^b1101; S6 = ^b1001; S10= ^b0101; S14= ^b0001;
S3 = ^b1100; S7 = ^b1000; S11= ^b0100; S15= ^b0000;
equations
[Q3,Q2,Q1,Q0].c = Clk;
[Q3,Q2,Q1,Q0].oe = !OE;
state_diagram [Q3,Q2,Q1,Q0]
State S0: IF !Clr THEN S1 ELSE S0;
State S1: IF !Clr THEN S2 ELSE S0;
State S2: IF !Clr THEN S3 ELSE S0;
State S3: IF !Clr THEN S4 ELSE S0;
State S4: IF !Clr THEN S5 ELSE S0;
State S5: IF !Clr THEN S6 ELSE S0;
State S6: IF !Clr THEN S7 ELSE S0;
State S7: IF !Clr THEN S8 ELSE S0;
State S8: IF !Clr THEN S9 ELSE S0;
State S9: GOTO S0;
"Ensure return from illegal state
State S10: GOTO S0;
State S11: GOTO S0;
State S12: GOTO S0;
State S13: GOTO S0;
State S14: GOTO S0;
State S15: GOTO S0;
@page
test_vectors 'Test Counter'
( [Clk ,OE, Clr ] -> [Q3,Q2,Q1,Q0])
[ Ck , 0, 1 ] -> S0;
[ Ck , 0, 0 ] -> S1;
[ Ck , 0, 0 ] -> S2;
[ Ck , 0, 0 ] -> S3;
[ Ck , 0, 0 ] -> S4;
[ Ck , 0, 0 ] -> S5;
[ Ck , 1, 0 ] -> Z ;
[ Ck , 0, 0 ] -> S7;
[ 0 , 0, 0 ] -> S7;
[ Ck , 0, 0 ] -> S8;
[ Ck , 0, 0 ] -> S9;
[ Ck , 0, 0 ] -> S0;
[ Ck , 0, 0 ] -> S1;
[ Ck , 0, 0 ] -> S2;
[ Ck , 0, 1 ] -> S0;
test_vectors 'preload to illegal states'
( [Clk ,OE, Clr,[Q3,Q2,Q1,Q0]] -> [Q3,Q2,Q1,Q0])
[ P , 1, 0 , S10 ] -> X ;
[ 0 , 0, 0 , X ] -> S10;
[ Ck , 0, 0 , X ] -> S0 ;
[ P , 1, 0 , S11 ] -> X ;
[ 0 , 0, 0 , X ] -> S11;
[ Ck , 0, 0 , X ] -> S0 ;
[ P , 1, 0 , S12 ] -> X ;
[ 0 , 0, 0 , X ] -> S12;
[ Ck , 0, 0 , X ] -> S0 ;
[ P , 1, 0 , S13 ] -> X ;
[ 0 , 0, 0 , X ] -> S13;
[ Ck , 0, 0 , X ] -> S0 ;
[ P , 1, 0 , S14 ] -> X ;
[ 0 , 0, 0 , X ] -> S14;
[ Ck , 0, 0 , X ] -> S0 ;
[ P , 1, 0 , S15 ] -> X ;
[ 0 , 0, 0 , X ] -> S15;
[ Ck , 0, 0 , X ] -> S0 ;
end

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module cnt10rom
title 'Up/Down counter State Machine in Registered PROM
Bob LaTurner Data I/O Corp. 18 Mar 1992'
cnt10rom device 'RA10R8';
" The RA10R8 models the Cypress Cy7C235, AMD Am27S35 or AMD 63RS881
" Pin ABEL Device
" 21 - N/C Combinatoral Enable
" 20 - N/C Initialize
" 19 - Enable Registered Enable
" 18 - Clock Clock
Clr,Dir,Clk,OE pin 3,4,18,19;
I3,I2,I1,I0 pin 5,6,7,8;
Q3,Q2,Q1,Q0 pin 13,11,10,9 ;
" Inputs I3..I0 are the external feedback from registers Q3..Q0.
Input = [I3,I2,I1,I0];
Output = [Q3,Q2,Q1,Q0];
C,X,Z = .C.,.X., .Z.;
" Counter States
S0 = 0; S1 = 1; S2 = 2; S3 = 3; S4 = 4;
S5 = 5; S6 = 6; S7 = 7; S8 = 8; S9 = 9;
" Counter modes
Mode = [Clr,Dir];
Up = [ 1 , 1 ];
Down = [ 1 , 0 ];
Clear = [ 0 , X ];
" The ABEL device file allows for up to 16 bytes for initializion
" as found in the 63RS881. The Cy7C235 and Am27S35 only use one byte
" but the extra will be ignored by the PROM programmer.
"
" ABEL does not simulate the initialization function.
"
" This FUSES section will set the initialization words to force the
" device to power up in state S9. A different value could be used
" for each of the 16 words. To see the fuse numbers, Compile with
" Expanded Listing option and then View Compiler Listing.
fuses @const a = 1024 * 8;
@repeat 16 {
[@expr a; .. @expr a + 7;] = S9; @const a = a + 8;}
test_vectors ( [Clk,OE, Mode ,Input] -> Output)
[ C , 0, Clear, X ] -> S0;
[ C , 0, Up , S0 ] -> S1;
[ C , 0, Up , S1 ] -> S2;
[ C , 0, Up , S2 ] -> S3;
[ C , 0, Up , S3 ] -> S4;
[ C , 0, Up , S4 ] -> S5;
[ C , 0, Up , S5 ] -> S6;
[ 0 , 0, Up , X ] -> S6;
[ C , 0, Up , S6 ] -> S7;
[ C , 0, Up , S7 ] -> S8;
[ C , 0, Up , S8 ] -> S9;
[ C , 0, Up , S9 ] -> S0;
[ C , 0, Up , S0 ] -> S1;
[ C , 0, Down , S1 ] -> S0;
[ C , 0, Down , S0 ] -> S9;
[ C , 1, Down , S9 ] -> Z ;
[ C , 0, Down , S8 ] -> S7;
[ C , 0, Clear, X ] -> S0;
Equations
Output.clk = Clk;
Output.oe = !OE;
state_diagram Input->Output
State S0: case (Mode == Up) : S1;
(Mode == Down) : S9;
(Mode == Clear) : S0;
endcase;
State S1: case (Mode == Up) : S2;
(Mode == Down) : S0;
(Mode == Clear) : S0;
endcase;
State S2: case (Mode == Up) : S3;
(Mode == Down) : S1;
(Mode == Clear) : S0;
endcase;
State S3: case (Mode == Up) : S4;
(Mode == Down) : S2;
(Mode == Clear) : S0;
endcase;
State S4: case (Mode == Up) : S5;
(Mode == Down) : S3;
(Mode == Clear) : S0;
endcase;
State S5: case (Mode == Up) : S6;
(Mode == Down) : S4;
(Mode == Clear) : S0;
endcase;
State S6: case (Mode == Up) : S7;
(Mode == Down) : S5;
(Mode == Clear) : S0;
endcase;
State S7: case (Mode == Up) : S8;
(Mode == Down) : S6;
(Mode == Clear) : S0;
endcase;
State S8: case (Mode == Up) : S9;
(Mode == Down) : S7;
(Mode == Clear) : S0;
endcase;
State S9: case (Mode == Up) : S0;
(Mode == Down) : S8;
(Mode == Clear) : S0;
endcase;
end

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module _cnt507
title 'TexIns PSG507 FPLS counter test case
Michael Holley Data I/O Corp 7 Dec 1987'
cnt507 device 'F507';
CK pin 1; VCC pin 24;
I02 pin 2; I23 pin 23;
I03 pin 3; I22 pin 22;
I04 pin 4; I21 pin 21;
I05 pin 5; I20 pin 20;
I06 pin 6; I19 pin 19;
I07 pin 7; I18 pin 18;
Q08 pin 8; OE17 pin 17;
Q09 pin 9; Q16 pin 16;
Q10 pin 10; Q15 pin 15;
Q11 pin 11; Q14 pin 14;
GND pin 12; Q13 pin 13;
SClr0, SClr1 node 25,26; " counter reset
CtHd0, CtHd1 node 28,29; " counter !HOLD
" Counter bits, input to AND-array
C0,C1,C2,C3,C4,C5 node 55,56,57,58,59,60;
" Buried SR-regs
P0,P1,P2,P3,P4,P5,P6,P7 node 31,32,33,34,35,36,37,38;
C,H,L,X,Z = .C.,1,0,.X.,.Z.;
counter = [C5,C4,C3,C2,C1,C0];
countout = [Q14,Q13,Q11,Q10,Q09,Q08];
equations
" 6-Bit counter conrtol function table
" SClr0 SClr1 CtHd0 CtHd1 Ctr.Ctrl
" L L L L count active
" H X X X sync clear
" X H X X sync clear
" L L H X hold counter
" L L X H hold counter
SClr0 = I02; "Combinatoral Clear
SClr1.S = I03; "Registered Clear
SClr1.R = I04;
CtHd0 = I05; "Combinatoral Hold
CtHd1.S = I06; "Registered Hold
CtHd1.R = I07;
countout.oe = !OE17;
countout = counter;
test_vectors
([CK,OE17, I02,I03,I04, I05,I06,I07] -> countout);
[ C, 0 , 1 , 0 , 1 , 1 , 0 , 1 ] -> X ; " poweron
[ C, 0 , 1 , 0 , 0 , 0 , 0 , 0 ] -> 0 ; " clear
[ C, 0 , 0 , 0 , 0 , 0 , 0 , 0 ] -> 1 ; " count
[ C, 0 , 0 , 0 , 0 , 0 , 0 , 0 ] -> 2 ; " count
[ C, 0 , 0 , 0 , 0 , 0 , 0 , 0 ] -> 3 ; " count
[ C, 0 , 0 , 0 , 0 , 0 , 0 , 0 ] -> 4 ; " count
[ C, 0 , 0 , 0 , 0 , 0 , 0 , 0 ] -> 5 ; " count
[ C, 0 , 0 , 0 , 0 , 0 , 0 , 0 ] -> 6 ; " count
[ C, 0 , 0 , 0 , 0 , 0 , 0 , 0 ] -> 7 ; " count
[ C, 0 , 0 , 0 , 0 , 1 , 0 , 0 ] -> 7 ; " hold (HLD0)
[ C, 0 , 0 , 0 , 0 , 1 , 0 , 0 ] -> 7 ; " hold
[ C, 0 , 0 , 0 , 0 , 0 , 0 , 0 ] -> 8 ; " count
[ C, 0 , 0 , 0 , 0 , 0 , 0 , 0 ] -> 9 ; " count
[ C, 0 , 0 , 0 , 0 , 0 , 0 , 0 ] -> 10 ; " count
[ C, 1 , 0 , 0 , 0 , 0 , 0 , 0 ] -> Z ; " count
[ C, 0 , 0 , 0 , 0 , 0 , 0 , 0 ] -> 12 ; " count
[ C, 0 , 0 , 0 , 0 , 0 , 1 , 0 ] -> 13 ; " hold (HLD1)
[ C, 0 , 0 , 0 , 0 , 0 , 0 , 0 ] -> 13 ; " hold (HLD1)
[ C, 0 , 0 , 0 , 0 , 0 , 0 , 1 ] -> 13 ; " hold (HLD1)
[ C, 0 , 0 , 0 , 0 , 0 , 0 , 0 ] -> 14 ; " count
[ 0, 0 , 0 , 0 , 0 , 0 , 0 , 0 ] -> 14 ; " no clock
[ C, 0 , 0 , 0 , 0 , 0 , 0 , 0 ] -> 15 ; " count
[ C, 0 , 1 , 0 , 0 , 0 , 0 , 0 ] -> 0 ; " clear
[ C, 0 , 0 , 0 , 0 , 0 , 0 , 0 ] -> 1 ; " count
[ C, 0 , 0 , 0 , 0 , 0 , 0 , 0 ] -> 2 ; " count
[ C, 0 , 0 , 0 , 0 , 0 , 0 , 0 ] -> 3 ; " count
[ C, 0 , 0 , 1 , 0 , 0 , 0 , 0 ] -> 4 ; " count
[ C, 0 , 0 , 0 , 0 , 0 , 0 , 0 ] -> 0 ; " clear
[ C, 0 , 0 , 0 , 1 , 0 , 0 , 0 ] -> 0 ; " clear
[ C, 0 , 0 , 0 , 0 , 0 , 0 , 0 ] -> 1 ; " count
[ C, 0 , 0 , 0 , 0 , 0 , 0 , 0 ] -> 2 ; " count
end _cnt507

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module cnt600
title '4 bit toggle flip flop counter
John Gromala 21 Sept 92, Data I/O Corporation'
cnt600 device 'e0600';
" Clk1 on pin 1 is used to clock pins 3 to 10 (unused)
" Clk2 on pin 13 is used to clock pins 15 to 22
" Inputs
Clk2 pin 13;
Dir,Ena,Clr pin 2, 3, 11;
" Outputs
Q3,Q2,Q1,Q0 pin 15,16,17,18 ISTYPE 'reg_t,buffer';
" Set assignment
Count = [Q3..Q0];
" Special Constants
X, Z, H, L = .X., .Z.,1 , 0;
equations "4 bit toggle flip flop counter
" Count Up
Q0.t = Dir;
Q1.t = Dir & Q0.q;
Q2.t = Dir & Q0.q & Q1.q;
Q3.t = Dir & Q0.q & Q1.q & Q2.q;
" Count Down
Q0.t = !Dir;
Q1.t = !Dir & !Q0.q;
Q2.t = !Dir & !Q0.q & !Q1.q;
Q3.t = !Dir & !Q0.q & !Q1.q & !Q2.q;
" Asychronous reset, Clock count from Clk2, Output enable
Count.AR = !Clr;
Count.CLK = Clk2;
Count.OE = Ena;
test_vectors 'Count Up'
([Clk2,Ena,Dir,Clr] -> Count)
[ L , 1 , H , L ] -> 0;
@const n = 0; @repeat 16 {
[ L , 1 , H , H ] -> @expr n; ; @const n = n+1;
[ H , 1 , H , H ] -> @expr n; ;}
[ L , 1 , H , H ] -> @expr n; ;
test_vectors 'Count Down'
([Clk2,Ena,Dir,Clr] -> Count)
@repeat 6 {
[ L , 1 , L , H ] -> @expr n; ; @const n = n-1;
[ H , 1 , L , H ] -> @expr n; ;}
[ L , 1 , L , H ] -> @expr n; ;
[ L , 1 , L , L ] -> 0;
end

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module CNTBUF
title 'Counter and Bidirectional Buffer
Dennis Freidman and John Gromala 21 Sept 1992, Data I/O Corporation'
cntbuf device 'E0320';
" Inputs
Clk, Clr, Dir, OE pin 1, 2, 3, 11;
" Outputs
Q3,Q2,Q1,Q0 pin 14, 15, 16, 17;
Q3,Q2,Q1,Q0 ISTYPE 'reg,buffer';
A1,A0,B1,B0 pin 12, 13, 18, 19;
A1,A0,B1,B0 ISTYPE 'com';
" Special Constants
C, X, Z = .C. , .X., .Z.;
" Set assignments
A = [A1,A0];
B = [B1,B0];
Count = [Q3..Q0];
equations
Count.OE = !OE;
Count.Clk = Clk;
Count := (Count.fb + 1) & !Clr;
trace ([Clk,OE,Clr,Dir] -> [Count,A,B])
test_vectors 'Counter'
([Clk,OE,Clr] -> Count)
[ C , 0, 1 ] -> 0;
[ C , 0, 0 ] -> 1;
[ C , 0, 0 ] -> 2;
[ C , 0, 0 ] -> 3;
[ C , 1, 0 ] -> Z;
[ C , 0, 0 ] -> 5;
[ C , 0, 0 ] -> 6;
[ C , 0, 0 ] -> 7;
[ C , 0, 0 ] -> 8;
[ C , 0, 0 ] -> 9;
[ C , 0, 0 ] -> 10;
[ C , 0, 0 ] -> 11;
[ C , 0, 0 ] -> 12;
[ C , 0, 0 ] -> 13;
[ C , 0, 0 ] -> 14;
[ C , 0, 0 ] -> 15;
[ C , 0, 0 ] -> 0;
[ C , 0, 0 ] -> 1;
[ C , 0, 0 ] -> 2;
[ C , 0, 0 ] -> 3;
[ C , 0, 1 ] -> 0;
[ C , 0, 1 ] -> 0;
equations
A.OE = Dir;
B.OE = !Dir;
A = B.pin; "Combinatorial signal can only have pin feedback
B = A.pin; "for this device.
trace([Clk,OE,Clr,Dir]-> [Count,A,B]);
test_vectors 'Buffer'
([ A , B ,Dir] -> [ A , B ])
[ X , X , 0 ] -> [ Z , X ];
[ X , X , 1 ] -> [ X , Z ];
[^h0, X , 0 ] -> [ X ,^h0];
[^h1, X , 0 ] -> [ X ,^h1];
[^h2, X , 0 ] -> [ X ,^h2];
[^h3, X , 0 ] -> [ X ,^h3];
[ X ,^h0, 1 ] -> [^h0, X ];
[ X ,^h1, 1 ] -> [^h1, X ];
[ X ,^h2, 1 ] -> [^h2, X ];
[ X ,^h3, 1 ] -> [^h3, X ];
end

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module comp4
title '4-bit look-ahead comparator
Charles Olivier & Mary Bailey Data I/O Corp. 24 Feb 1984'
IC1 device 'P16HD8';
A3,A2,A1,A0 pin 1,2,3,4;
B3,B2,B1,B0 pin 5,6,7,8;
E3,E2,E1,E0 pin 14,15,16,17;
A_NE_B,A_EQ_B pin 12,13;
A_GT_B,A_LT_B pin 18,19;
No,Yes = 0,1;
A = [A3,A2,A1,A0];
B = [B3,B2,B1,B0];
E = [E3,E2,E1,E0];
C0 macro {(A0>B0)};
C1 macro {(A1>B1) # E1 & (C0)};
C2 macro {(A2>B2) # E2 & (C1)};
equations
E = A !$ B; "intermediate An = Bn
A_EQ_B = E3 & E2 & E1 & E0;
A_NE_B = !A_EQ_B;
A_GT_B = (A3>B3) # E3 & (C2);
A_LT_B = !A_GT_B & !A_EQ_B;
test_vectors 'test for A = B'
([ A, B] -> [A_EQ_B, A_GT_B, A_LT_B, A_NE_B])
[ 0, 0] -> [ Yes , No , No , No ];
[ 1, 1] -> [ Yes , No , No , No ];
[ 2, 2] -> [ Yes , No , No , No ];
[ 5, 5] -> [ Yes , No , No , No ];
[ 8, 8] -> [ Yes , No , No , No ];
[10,10] -> [ Yes , No , No , No ];
[15,15] -> [ Yes , No , No , No ];
test_vectors 'test for A > B'
([ A, B] -> [A_EQ_B, A_GT_B, A_LT_B, A_NE_B])
[ 1, 0] -> [ No , Yes , No , Yes ];
[ 2, 1] -> [ No , Yes , No , Yes ];
[ 4, 3] -> [ No , Yes , No , Yes ];
[ 8, 7] -> [ No , Yes , No , Yes ];
[15,14] -> [ No , Yes , No , Yes ];
[ 6, 2] -> [ No , Yes , No , Yes ];
[ 5, 0] -> [ No , Yes , No , Yes ];
test_vectors 'test for A < B'
([ A, B] -> [A_EQ_B, A_GT_B, A_LT_B, A_NE_B])
[ 3, 9] -> [ No , No , Yes , Yes ];
[14,15] -> [ No , No , Yes , Yes ];
[ 7, 8] -> [ No , No , Yes , Yes ];
[ 3, 4] -> [ No , No , Yes , Yes ];
[ 2, 8] -> [ No , No , Yes , Yes ];
end comp4

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module COMP4A
title '4-bit look-ahead comparator 5 June 1990
Steve Weil & Gary Thomas Data I/O Corp.'
comp4a device 'F153';
A3,A2,A1,A0 pin 1,2,3,4; A = [A3,A2,A1,A0];
B3,B2,B1,B0 pin 5,6,7,8; B = [B3,B2,B1,B0];
A_NE_B,A_EQ_B,A_GT_B,A_LT_B pin 16,17,18,19;
A_EQ_B istype 'neg';
No,Yes = 0,1;
equations
A_EQ_B = A == B;
A_NE_B = !(A == B);
A_GT_B = A > B;
A_LT_B = !((A > B) # (A == B));
test_vectors 'test for A = B'
([ A, B] -> [A_EQ_B, A_GT_B, A_LT_B, A_NE_B])
[ 0, 0] -> [ Yes , No , No , No ];
[ 1, 1] -> [ Yes , No , No , No ];
[ 2, 2] -> [ Yes , No , No , No ];
[ 5, 5] -> [ Yes , No , No , No ];
[ 8, 8] -> [ Yes , No , No , No ];
[10,10] -> [ Yes , No , No , No ];
[15,15] -> [ Yes , No , No , No ];
test_vectors 'test for A > B'
([ A, B] -> [A_EQ_B, A_GT_B, A_LT_B, A_NE_B])
[ 1, 0] -> [ No , Yes , No , Yes ];
[ 2, 1] -> [ No , Yes , No , Yes ];
[ 4, 3] -> [ No , Yes , No , Yes ];
[ 8, 7] -> [ No , Yes , No , Yes ];
[15,14] -> [ No , Yes , No , Yes ];
[ 6, 2] -> [ No , Yes , No , Yes ];
[ 5, 0] -> [ No , Yes , No , Yes ];
test_vectors 'test for A < B'
([ A, B] -> [A_EQ_B, A_GT_B, A_LT_B, A_NE_B])
[ 3, 9] -> [ No , No , Yes , Yes ];
[14,15] -> [ No , No , Yes , Yes ];
[ 7, 8] -> [ No , No , Yes , Yes ];
[ 3, 4] -> [ No , No , Yes , Yes ];
[ 2, 8] -> [ No , No , Yes , Yes ];
end

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MODULE control
TITLE 'Traffic Signal Controller - Data I/O Corp.'
Clk,SenA,SenB PIN;
Pr PIN; "Preset control
Ga,Ya,Ra PIN ISTYPE 'BUFFER';
Gb,Yb,Rb PIN ISTYPE 'BUFFER';
s3,s2,s1,s0 NODE;
s3,s2,s1,s0 ISTYPE 'BUFFER,REG_RS';
H,L,Ck,X = 1, 0, .C., .X.;
Count = [s3,s2,s1,s0];
"Define Set and Reset inputs to traffic light flip flops
GreenA = [Ga.S,Ga.R];
YellowA = [Ya.S,Ya.R];
RedA = [Ra.S,Ra.R];
GreenB = [Gb.S,Gb.R];
YellowB = [Yb.S,Yb.R];
RedB = [Rb.S,Rb.R];
On = [ 1 , 0 ];
Off = [ 0 , 1 ];
TEST_VECTORS
([Clk,Pr,SenA,SenB] -> [Count,Ga,Ya,Ra,Gb,Yb,Rb])
[ 0 , 0, 0 , 0 ] -> [ X , X, X, X, X, X, X];
[ 1 , 1, 1 , 1 ] -> [ 15 , X, X, X, X, X, X];
[ 1 , 0, 1 , 1 ] -> [ 15 , X, X, X, X, X, X];
[ Ck, 0, 1 , 0 ] -> [ 0 , H, L, L, L, L, H];
TEST_VECTORS
([Clk,Pr,SenA,SenB] -> [Count,Ga,Ya,Ra,Gb,Yb,Rb])
[ Ck, 0, 1 , 0 ] -> [ 0 , H, L, L, L, L, H];
[ Ck, 0, 1 , 0 ] -> [ 0 , H, L, L, L, L, H];
[ Ck, 0, 1 , 1 ] -> [ 1 , H, L, L, L, L, H];
[ Ck, 0, 1 , 1 ] -> [ 2 , H, L, L, L, L, H];
[ Ck, 0, 1 , 1 ] -> [ 3 , H, L, L, L, L, H];
[ Ck, 0, 1 , 1 ] -> [ 4 , H, L, L, L, L, H];
[ Ck, 0, 1 , 1 ] -> [ 5 , L, H, L, L, L, H];
[ Ck, 0, 1 , 0 ] -> [ 8 , L, L, H, H, L, L];
[ Ck, 0, 1 , 0 ] -> [ 12 , L, L, H, H, L, L];
[ Ck, 0, 1 , 0 ] -> [ 13 , L, L, H, L, H, L];
[ Ck, 0, 1 , 0 ] -> [ 0 , H, L, L, L, L, H];
[ Ck, 0, 1 , 0 ] -> [ 0 , H, L, L, L, L, H];
[ Ck, 0, 1 , 1 ] -> [ 1 , H, L, L, L, L, H];
[ Ck, 0, 1 , 1 ] -> [ 2 , H, L, L, L, L, H];
[ Ck, 0, 1 , 1 ] -> [ 3 , H, L, L, L, L, H];
[ 1 , 1, 1 , 1 ] -> [ 15 , X, X, X, X, X, X];
[ 1 , 0, 1 , 1 ] -> [ 15 , X, X, X, X, X, X];
[ Ck, 0, 1 , 0 ] -> [ 0 , H, L, L, L, L, H];
@PAGE
EQUATIONS
[Gb,Yb,Rb].AP = Pr;
[Ga,Ya,Ra].AP = Pr;
[Gb,Yb,Rb].CLK = Clk;
[Ga,Ya,Ra].CLK = Clk;
[s3,s2,s1,s0].AP = Pr;
[s3,s2,s1,s0].CLK = Clk;
@DCSET
STATE_DIAGRAM Count
STATE 0: IF ( SenA & !SenB ) THEN 0;
IF (!SenA & SenB ) THEN 4;
IF ( SenA == SenB ) THEN 1;
STATE 1: GOTO 2;
STATE 2: GOTO 3;
STATE 3: GOTO 4;
STATE 4: GreenA = Off;
YellowA = On ;
GOTO 5;
STATE 5: YellowA = Off;
RedA = On ;
RedB = Off;
GreenB = On ;
GOTO 8;
STATE 8: IF (!SenA & SenB ) THEN 8;
IF ( SenA & !SenB ) THEN 12;
IF ( SenA == SenB ) THEN 9;
STATE 9: GOTO 10;
STATE 10: GOTO 11;
STATE 11: GOTO 12;
STATE 12: GreenB = Off;
YellowB = On ;
GOTO 13;
STATE 13: YellowB = Off;
RedB = On ;
RedA = Off;
GreenA = On ;
GOTO 0;
STATE 15: "Power up and preset state
RedA = Off;
YellowA = Off;
GreenA = On ;
RedB = On ;
YellowB = Off;
GreenB = Off;
GOTO 0;
"Unused states
" STATE 6: GOTO 0;
" STATE 7: GOTO 0;
" STATE 14: GOTO 0;
END control

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Module Count116
Title 'Arbitrary length counter with Carry Out
Michael Holley Data I/O Corp 30 May 1990'
count116 device 'P16R8';
Osc,IncAdr,ClrAdr,OE pin 1,3,2,11;
!A6,!A5,!A4,!A3,!A2,!A1,!A0 pin 18,17,16,15,14,13,12;
!CarryA pin 19;
" Note that the outputs are active low.
H,L,Z,X,C = 1, 0, .Z., .X., .C.;
CountA = [A6,A5,A4,A3,A2,A1,A0];
" This counter uses registered look ahead carry to implement an
" arbitrary length count.
" The D input to the CarryA register will be high at the 115 count.
" On the next clock with IncAdr high the CarryA will be set and
" the count will advance to 116.
" The counter keep incrementing as long a CarryA is low, so the
" counter will return to 0 on the next clock with IncAdr high.
Equations
CountA := (CountA.fb + 1) & IncAdr & ClrAdr & !CarryA.fb
# CountA.fb & !IncAdr & ClrAdr;
CarryA := (CountA.fb == 115) & IncAdr & ClrAdr
# CarryA.fb & !IncAdr & ClrAdr;
CountA.clk = Osc;
CountA.oe = !OE;
CarryA.clk = Osc;
CarryA.oe = !OE;
test_vectors
([Osc,OE,ClrAdr,IncAdr] -> [CarryA,CountA])
[ C , 0, 0 , 1 ] -> [ 0 , 0 ];
[ C , 0, 1 , 1 ] -> [ 0 , 1 ];
[ C , 0, 1 , 1 ] -> [ 0 , 2 ];
[ C , 0, 1 , 1 ] -> [ 0 , 3 ];
[ C , 0, 1 , 1 ] -> [ 0 , 4 ];
[ C , 0, 1 , 1 ] -> [ 0 , 5 ];
[ C , 0, 1 , 0 ] -> [ 0 , 5 ];
[ C , 0, 1 , 1 ] -> [ 0 , 6 ];
[ C , 0, 0 , 1 ] -> [ 0 , 0 ];
@const i=1; @repeat 112 {
[ C , 0, 1 , 1 ] -> [ 0 , @expr i; ]; @const i=i+1;}
[ C , 0, 1 , 1 ] -> [ 0 , 113 ];
[ C , 0, 1 , 1 ] -> [ 0 , 114 ];
[ C , 0, 1 , 1 ] -> [ 0 , 115 ];
[ C , 0, 1 , 0 ] -> [ 0 , 115 ];
[ C , 0, 1 , 1 ] -> [ 1 , 116 ];
[ C , 0, 1 , 0 ] -> [ 1 , 116 ];
[ C , 0, 1 , 1 ] -> [ 0 , 0 ];
[ C , 0, 1 , 1 ] -> [ 0 , 1 ];
end

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module COUNT4
title '4-bit counter with 2 input mux 12 Oct 1992
based on an example by Birkner/Coli in the MMI PAL Handbook
Dan Burrier & Mike McGee Data I/O Corp.'
count4 device 'P16R4';
Clk,OC,I1,I0,CI pin 1,11,13,18,19;
A0,A1,A2,A3,B0,B1,B2,B3 pin 2,3,4,5,6,7,8,9;
Q3,Q2,Q1,Q0 pin 14,15,16,17 istype 'reg,invert';
CO pin 12 istype 'com';
H,L,X,Z,C = 1,0, .X.,.Z.,.C.;
InputA = [A3,A2,A1,A0];
InputB = [B3,B2,B1,B0];
Output = [CO,Q3,Q2,Q1,Q0];
Mode = [I1,I0];
Hold,LoadA,LoadB,Incr = 0,1,2,3; " define Modes
equations
[Q3..Q0].clk = Clk;
[Q3..Q0].oe = !OC;
!Q0 := (Mode==Hold ) & !Q0.fb
# (Mode==LoadA) & !A0
# (Mode==LoadB) & !B0
# (Mode==Incr ) & !CI & !Q0.fb "Hold if no carry
# (Mode==Incr ) & CI & Q0.fb;
!Q1 := (Mode==Hold ) & !Q1.fb
# (Mode==LoadA) & !A1
# (Mode==LoadB) & !B1
# (Mode==Incr ) & !CI & !Q1.fb "Hold if no carry
# (Mode==Incr ) & !Q0.fb & !Q1.fb "Hold if Q0=L
# (Mode==Incr ) & CI & Q0.fb & Q1.fb;
!Q2 := (Mode==Hold ) & !Q2.fb
# (Mode==LoadA) & !A2
# (Mode==LoadB) & !B2
# (Mode==Incr ) & !CI & !Q2.fb "Hold if no carry
# (Mode==Incr ) & !Q0.fb & !Q2.fb "Hold if Q0=L
# (Mode==Incr ) & !Q1.fb & !Q2.fb "Hold if Q1=L
# (Mode==Incr ) & CI & Q0.fb & Q1.fb & Q2.fb;
!Q3 := (Mode==Hold ) & !Q3.fb
# (Mode==LoadA) & !A3
# (Mode==LoadB) & !B3
# (Mode==Incr ) & !CI & !Q3.fb "Hold if no carry
# (Mode==Incr ) & !Q0.fb & !Q3.fb "Hold if Q0=L
# (Mode==Incr ) & !Q1.fb & !Q3.fb "Hold if Q1=L
# (Mode==Incr ) & !Q2.fb & !Q3.fb "Hold if Q2=L
# (Mode==Incr ) & CI & Q0.fb & Q1.fb & Q2.fb & Q3.fb;
!CO = !CI # !Q0.fb # !Q1.fb # !Q2.fb # !Q3.fb;
@page
test_vectors ' test Load A and B'
([Clk,OC, Mode, InputA, InputB,CI ] -> Output)
[ C, L, LoadA, ^h0 , ^hF ,X ] -> ^h0;
[ C, L, LoadB, ^h0 , ^hF ,L ] -> ^hF;
[ C, L, LoadA, ^h1 , ^h7 ,X ] -> ^h1;
[ C, L, LoadB, ^h1 , ^h7 ,X ] -> ^h7;
[ C, L, LoadA, ^h2 , ^hB ,X ] -> ^h2;
[ C, L, LoadB, ^h2 , ^hB ,X ] -> ^hB;
[ C, L, LoadA, ^h4 , ^hD ,X ] -> ^h4;
[ C, L, LoadB, ^h4 , ^hD ,X ] -> ^hD;
[ C, L, LoadA, ^h8 , ^hE ,X ] -> ^h8;
[ C, L, LoadB, ^h8 , ^hE ,X ] -> ^hE;
[ C, L, LoadA, ^h0 , ^hF ,X ] -> ^h0;
[ C, L, LoadB, ^h0 , ^hF ,L ] -> ^hF;
test_vectors ' test increment'
([Clk,OC, Mode, InputA, InputB,CI ] -> Output)
[ C, L, LoadB, X , ^h1 ,X ] -> ^h1;
[ C, L, Incr , X , X ,H ] -> ^h2;
[ C, L, LoadB, X , ^h3 ,X ] -> ^h3;
[ C, L, Incr , X , X ,H ] -> ^h4;
[ C, L, LoadA, ^h7 , X ,X ] -> ^h7;
[ C, L, Incr , X , X ,H ] -> ^h8;
[ C, L, LoadA, ^hF , X ,L ] -> ^hF;
[ C, L, Incr , X , X ,H ] -> ^h0; "roll over
[ C, L, LoadB, X , ^hC ,X ] -> ^hC;
[ C, L, Incr , X , X ,H ] -> ^hD;
[ C, L, Hold , X , X ,H ] -> ^hD;
test_vectors ' test carry'
([Clk,OC, Mode, InputA, InputB,CI ] -> Output)
[ C, L, Incr , X , X ,H ] -> ^hE;
[ C, L, Incr , X , X ,H ] -> ^h1F; "carry out
[ C, L, Incr , X , X ,H ] -> ^h0; "roll over
[ C, L, Incr , X , X ,H ] -> ^h1;
[ C, L, Incr , X , X ,L ] -> ^h1; "no carry in
[ C, L, Incr , X , X ,H ] -> ^h2;
[ L, H, Hold , X , X ,X ] -> [X,Z,Z,Z,Z];
end COUNT4

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module COUNT4A
title '4-bit counter with 2 input mux 9 Aug 1990
based on an example by Birkner/Coli in the MMI PAL Handbook
Lisa Matheson Data I/O Corp.'
count4a device 'P16R4';
Clk,OC,CO,I1,I0,CI pin 1,11,12,13,18,19;
A0,A1,A2,A3,B0,B1,B2,B3 pin 2,3,4,5,6,7,8,9;
Q3,Q2,Q1,Q0 pin 14,15,16,17;
H,L,X,Z,C = 1,0, .X.,.Z.,.C.;
InputA = [A3,A2,A1,A0];
InputB = [B3,B2,B1,B0];
Output = [CO,Q3,Q2,Q1,Q0];
Mode = [I1,I0];
Hold,LoadA,LoadB,Incr = 0,1,2,3; " define Modes
equations " global
[Q3..Q0].clk = Clk;
[Q3..Q0].oe = !OC;
equations " input multiplexer
!Q0 := (Mode==Hold ) & !Q0
# (Mode==LoadA) & !A0
# (Mode==LoadB) & !B0;
!Q1 := (Mode==Hold ) & !Q1
# (Mode==LoadA) & !A1
# (Mode==LoadB) & !B1;
!Q2 := (Mode==Hold ) & !Q2
# (Mode==LoadA) & !A2
# (Mode==LoadB) & !B2;
!Q3 := (Mode==Hold ) & !Q3
# (Mode==LoadA) & !A3
# (Mode==LoadB) & !B3;
" 4 bit counter
!Q0 := (Mode==Incr ) & !CI & !Q0 "Hold if no carry
# (Mode==Incr ) & CI & Q0 ;
!Q1 := (Mode==Incr ) & !CI & !Q1 "Hold if no carry
# (Mode==Incr ) & !Q0 & !Q1 "Hold if Q0=L
# (Mode==Incr ) & CI & Q0 & Q1 ;
!Q2 := (Mode==Incr ) & !CI & !Q2 "Hold if no carry
# (Mode==Incr ) & !Q0 & !Q2 "Hold if Q0=L
# (Mode==Incr ) & !Q1 & !Q2 "Hold if Q1=L
# (Mode==Incr ) & CI & Q0 & Q1 & Q2 ;
!Q3 := (Mode==Incr ) & !CI & !Q3 "Hold if no carry
# (Mode==Incr ) & !Q0 & !Q3 "Hold if Q0=L
# (Mode==Incr ) & !Q1 & !Q3 "Hold if Q1=L
# (Mode==Incr ) & !Q2 & !Q3 "Hold if Q2=L
# (Mode==Incr ) & CI & Q0 & Q1 & Q2 & Q3 ;
!CO = !CI # !Q0 # !Q1 # !Q2 # !Q3 ;
@page
test_vectors ' test Load A and B'
([Clk,OC, Mode, InputA, InputB,CI ] -> Output)
[ C, L, LoadA, ^h0 , ^hF ,X ] -> ^h0;
[ C, L, LoadB, ^h0 , ^hF ,L ] -> ^hF;
[ C, L, LoadA, ^h1 , ^h7 ,X ] -> ^h1;
[ C, L, LoadB, ^h1 , ^h7 ,X ] -> ^h7;
[ C, L, LoadA, ^h2 , ^hB ,X ] -> ^h2;
[ C, L, LoadB, ^h2 , ^hB ,X ] -> ^hB;
[ C, L, LoadA, ^h4 , ^hD ,X ] -> ^h4;
[ C, L, LoadB, ^h4 , ^hD ,X ] -> ^hD;
[ C, L, LoadA, ^h8 , ^hE ,X ] -> ^h8;
[ C, L, LoadB, ^h8 , ^hE ,X ] -> ^hE;
[ C, L, LoadA, ^h0 , ^hF ,X ] -> ^h0;
[ C, L, LoadB, ^h0 , ^hF ,L ] -> ^hF;
test_vectors ' test increment'
([Clk,OC, Mode, InputA, InputB,CI ] -> Output)
[ C, L, LoadB, X , ^h1 ,X ] -> ^h1;
[ C, L, Incr , X , X ,H ] -> ^h2;
[ C, L, LoadB, X , ^h3 ,X ] -> ^h3;
[ C, L, Incr , X , X ,H ] -> ^h4;
[ C, L, LoadA, ^h7 , X ,X ] -> ^h7;
[ C, L, Incr , X , X ,H ] -> ^h8;
[ C, L, LoadA, ^hF , X ,L ] -> ^hF;
[ C, L, Incr , X , X ,H ] -> ^h0; "roll over
[ C, L, LoadB, X , ^hC ,X ] -> ^hC;
[ C, L, Incr , X , X ,H ] -> ^hD;
[ C, L, Hold , X , X ,H ] -> ^hD;
test_vectors ' test carry'
([Clk,OC, Mode, InputA, InputB,CI ] -> Output)
[ C, L, Incr , X , X ,H ] -> ^hE;
[ C, L, Incr , X , X ,H ] -> ^h1F; "carry out
[ C, L, Incr , X , X ,H ] -> ^h0; "roll over
[ C, L, Incr , X , X ,H ] -> ^h1;
[ C, L, Incr , X , X ,L ] -> ^h1; "no carry in
[ C, L, Incr , X , X ,H ] -> ^h2;
[ L, H, Hold , X , X ,X ] -> [X,Z,Z,Z,Z];
end COUNT4A

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MODULE counter;
DECLARATIONS;
q3,q2,q1,q0 PIN 17,16,15,14;
oe,clock,reset PIN;
count = [q3 .. q0];
EQUATIONS;
count := (count.fb + 1) & (count.fb < 9) & (!reset);
count.clk = clock;
count.oe = !oe;
TEST_VECTORS ([clock,reset] -> count);
[ .c. , 1 ] -> 0;
[ .c. , 0 ] -> 1;
[ .c. , 0 ] -> 2;
[ .c. , 0 ] -> 3;
[ .c. , 0 ] -> 4;
[ .c. , 0 ] -> 5;
[ .c. , 0 ] -> 6;
[ .c. , 0 ] -> 7;
[ .c. , 0 ] -> 8;
[ .c. , 0 ] -> 9;
[ .c. , 1 ] -> 0;
[ .c. , 0 ] -> 1;
[ .c. , 0 ] -> 2;
[ .c. , 1 ] -> 0;
[ .c. , 0 ] -> 1;
[ .c. , 0 ] -> 2;
END counter;

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module DECADE
title 'Decade Counter Uses Complement Array
Bob Hamilton Data I/O Corp 13 Aug 1990'
decade device 'F105';
Clk,Clr,F0,PR pin 1,8,18,19;
P3,P2,P1,P0 node 40,39,38,37;
COMP node 49;
F0,P3,P2,P1,P0 istype 'reg_rs';
_State = [P3,P2,P1,P0];
H,L,Ck,X = 1, 0, .C., .X.;
equations
[P3,P2,P1,P0,F0].ap = PR;
[F0,P3,P2,P1,P0].clk = Clk;
"Output Next State Present State Input
[F0.S, COMP, P0.S] = !P3 & !P2 & !P1 & !P0 & !Clr; "0 to 1
[ COMP, P1.S,P0.R] = !P3 & !P2 & !P1 & P0 & !Clr; "1 to 2
[ COMP, P0.S] = !P3 & !P2 & P1 & !P0 & !Clr; "2 to 3
[ COMP, P2.S,P1.R,P0.R] = !P3 & !P2 & P1 & P0 & !Clr; "3 to 4
[ COMP, P0.S] = !P3 & P2 & !P1 & !P0 & !Clr; "4 to 5
[F0.R, COMP, P1.S,P0.R] = !P3 & P2 & !P1 & P0 & !Clr; "5 to 6
[ COMP, P0.S] = !P3 & P2 & P1 & !P0 & !Clr; "6 to 7
[ COMP,P3.S,P2.R,P1.R,P0.R] = !P3 & P2 & P1 & P0 & !Clr; "7 to 8
[ COMP, P0.S] = P3 & !P2 & !P1 & !P0 & !Clr; "8 to 9
[ P3.R,P2.R,P1.R,P0.R] = !COMP; "Clear
"After Preset, clocking is inhibited until a High-to-Low clock transition.
test_vectors ([Clk,PR,Clr] -> [_State,F0 ])
[ 0 , 0, 0 ] -> [ X , X];
[ 1 , 1, 0 ] -> [^b1111, H]; " Preset high
[ 1 , 0, 0 ] -> [^b1111, H]; " Preset low
[ Ck, 0, 0 ] -> [ 0 , H]; " COMP forces to State 0
[ Ck, 0, 0 ] -> [ 1 , H];
[ Ck, 0, 0 ] -> [ 2 , H];
[ Ck, 0, 0 ] -> [ 3 , H];
[ Ck, 0, 0 ] -> [ 4 , H];
[ Ck, 0, 0 ] -> [ 5 , H];
[ Ck, 0, 0 ] -> [ 6 , L];
[ Ck, 0, 0 ] -> [ 7 , L];
[ Ck, 0, 0 ] -> [ 8 , L];
[ Ck, 0, 0 ] -> [ 9 , L];
[ Ck, 0, 0 ] -> [ 0 , L];
[ Ck, 0, 0 ] -> [ 1 , H];
[ Ck, 0, 0 ] -> [ 2 , H];
[ Ck, 0, 1 ] -> [ 0 , H]; " Clear
end

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trunk/workspace/01_EasyAbel/AHDL/DECODER.ABL Normal file
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MODULE decoder;
TITLE 'Memory decoder - Data I/O Corp, Redmond WA';
DECLARATIONS
a15,a14,a13,a12,a11,a10 PIN;
rom1,io,rom2,dram PIN;
h,l,x = 1,0,.X.;
address = [a15,a14,a13,a12, a11,a10,x,x, x,x,x,x, x,x,x,x];
EQUATIONS
!dram = (address <= ^hdfff);
!io = (address >= ^he000) & (address <= ^he7ff);
!rom2 = (address >= ^hf000) & (address <= ^hf7ff);
!rom1 = (address >= ^hf800);
TEST_VECTORS
(address -> [rom1,rom2,io,dram]);
^h0000 -> [ h, h, h, l ];
^h4000 -> [ h, h, h, l ];
^h8000 -> [ h, h, h, l ];
^hC000 -> [ h, h, h, l ];
^hE000 -> [ h, h, l, h ];
^hE800 -> [ h, h, h, h ];
^hF000 -> [ h, l, h, h ];
^hF800 -> [ l, h, h, h ];
END decoder;

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trunk/workspace/01_EasyAbel/AHDL/DECODER.DMC Normal file
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#$ SOURCEFILE DECODER.abl
#$ LISTFILE DECODER.lst
#$ MODULE decoder
#$ PLAFILE decoder.tt1
#$ JEDECFILE decoder

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Page 1
EZ-ABEL 4.30 - Device Utilization Chart Mon Apr 7 17:39:47 19;4
Memory decoder - Data I/O Corp, Redmond WA
==== P16P8 Programmed Logic ====
dram = ( a15 & a14 & a13 );
io = !( a15 & a14 & a13 & !a12 & !a11 );
rom2 = !( a15 & a14 & a13 & a12 & !a11 );
rom1 = !( a15 & a14 & a13 & a12 & a11 );
Page 2
EZ-ABEL 4.30 - Device Utilization Chart Mon Apr 7 17:39:47 19;4
Memory decoder - Data I/O Corp, Redmond WA
==== P16P8 Chip Diagram ====
P16P8
+---------\ /---------+
| \ / |
| ----- |
a15 | 1 20 | Vcc
| |
a14 | 2 19 | !rom1
| |
a13 | 3 18 | !io
| |
a12 | 4 17 | !dram
| |
a11 | 5 16 |
| |
| 6 15 |
| |
| 7 14 |
| |
| 8 13 |
| |
| 9 12 | !rom2
| |
GND | 10 11 |
| |
| |
`---------------------------'
SIGNATURE: N/A
Page 3
EZ-ABEL 4.30 - Device Utilization Chart Mon Apr 7 17:39:47 19;4
Memory decoder - Data I/O Corp, Redmond WA
==== P16P8 Resource Allocations ====
Device | Resource | Design | Part |
Resources | Available | Requirement | Utilization | Unused
======================|===========|=============|=============|==============
| | | |
Dedicated input pins | 10 | 5 | 5 | 5 ( 50 %)
Combinatorial inputs | 10 | 5 | 5 | 5 ( 50 %)
Registered inputs | - | 0 | - | -
| | | |
Dedicated output pins | 2 | 4 | 2 | 0 ( 0 %)
Bidirectional pins | 6 | 0 | 2 | 4 ( 66 %)
Combinatorial outputs | 8 | 4 | 4 | 4 ( 50 %)
Registered outputs | - | 0 | - | -
Two-input XOR | - | 0 | - | -
| | | |
Buried nodes | - | 0 | - | -
Buried registers | - | 0 | - | -
Buried combinatorials | - | 0 | - | -
Page 4
EZ-ABEL 4.30 - Device Utilization Chart Mon Apr 7 17:39:47 19;4
Memory decoder - Data I/O Corp, Redmond WA
==== P16P8 Product Terms Distribution ====
Signal | Pin | Terms | Terms | Terms
Name | Assigned | Used | Max | Unused
===============================|==========|=======|=======|=======
dram | 17 | 1 | 7 | 6
io | 18 | 1 | 7 | 6
rom2 | 12 | 1 | 7 | 6
rom1 | 19 | 1 | 7 | 6
==== List of Inputs/Feedbacks ====
Signal Name | Pin | Pin Type
============================== |==========|=========
a15 | 1 | INPUT
a14 | 2 | INPUT
a13 | 3 | INPUT
a12 | 4 | INPUT
a11 | 5 | INPUT
Page 5
EZ-ABEL 4.30 - Device Utilization Chart Mon Apr 7 17:39:47 19;4
Memory decoder - Data I/O Corp, Redmond WA
==== P16P8 Unused Resources ====
Pin | Pin | Product | Flip-flop
Number | Type | Terms | Type
=======|========|=============|==========
6 | INPUT | - | -
7 | INPUT | - | -
8 | INPUT | - | -
9 | INPUT | - | -
11 | INPUT | - | -
13 | BIDIR | NORMAL 7 | -
14 | BIDIR | NORMAL 7 | -
15 | BIDIR | NORMAL 7 | -
16 | BIDIR | NORMAL 7 | -
Page 6
EZ-ABEL 4.30 - Device Utilization Chart Mon Apr 7 17:39:47 19;4
Memory decoder - Data I/O Corp, Redmond WA
==== I/O Files ====
Module: 'decoder'
Input files
===========
ABEL PLA file: decoder.tt3
Vector file: decoder.tmv
Device library: P16P8.dev
Output files
============
Report file: decoder.doc
Programmer load file: decoder.jed

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$DEVICE p16p8 fit decoder.tt3
$PINS 9 rom1:19 rom2:12 io:18 dram:17 a11:5 a12:4 a13:3
a14:2 a15:1
--------------------------------------------------------------

28
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EZ-ABEL 4.32 Data I/O Corp. JEDEC file for: P16P8 V9.0
Created on: Mon Apr 7 17:39:47 19;4
Memory decoder - Data I/O Corp, Redmond WA
*
QP20* QF2056* QV8* F0*
X0*
NOTE Table of pin names and numbers*
NOTE PINS a15:1 a14:2 a13:3 a12:4 a11:5 rom1:19 io:18 rom2:12 dram:17*
L0000 11111111111111111111111111111111*
L0032 01010111011101111111111111111111*
L0256 11111111111111111111111111111111*
L0288 01010111101110111111111111111111*
L0512 11111111111111111111111111111111*
L0544 01010111111111111111111111111111*
L1792 11111111111111111111111111111111*
L1824 01010111011110111111111111111111*
L2048 00100000*
V0001 00000XXXXNXHXXXXLHHN*
V0002 01000XXXXNXHXXXXLHHN*
V0003 10000XXXXNXHXXXXLHHN*
V0004 11000XXXXNXHXXXXLHHN*
V0005 11100XXXXNXHXXXXHLHN*
V0006 11101XXXXNXHXXXXHHHN*
V0007 11110XXXXNXLXXXXHHHN*
V0008 11111XXXXNXHXXXXHHLN*
C1F3C*
C609

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